[PATCH] drm/xe/dg2: Fix number of mocs entries

[Lucas De Marchi]

While investigating why xe_mocs kunit was failing for DG2, Matt Roper
noticed that LNCFCMOCS[31] is actually RO for DG2. It would be a spec
bug to document a register to be programmed that is actually RO. However
upon further inspection, it seems like we should not be programming the
other values. Early DG2 SKUs documented that the entire set of
LNCFCMOCS registers needed to be programmed, but this is not true
anymore.

Do like is done in MTL: the additional registers are there, but we are
not supposed to program them, not even with the unused_index value.

While at it, fix MTL define to follow the same alignment as others, with
tabs.

Bspec: 44988, 55267
Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/1253
Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/1233
Cc: Matt Roper <matthew.d.roper at intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
---
 drivers/gpu/drm/xe/xe_mocs.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_mocs.c b/drivers/gpu/drm/xe/xe_mocs.c
index 609d997b3e9b0..bb28c26a46d5b 100644
--- a/drivers/gpu/drm/xe/xe_mocs.c
+++ b/drivers/gpu/drm/xe/xe_mocs.c
@@ -71,8 +71,9 @@ struct xe_mocs_info {
 
 /* Helper defines */
 #define XELP_NUM_MOCS_ENTRIES	64  /* 63-64 are reserved, but configured. */
+#define XEHP_NUM_MOCS_ENTRIES	4
 #define PVC_NUM_MOCS_ENTRIES	3
-#define MTL_NUM_MOCS_ENTRIES    16
+#define MTL_NUM_MOCS_ENTRIES	16
 #define XE2_NUM_MOCS_ENTRIES	16
 
 /* (e)LLC caching options */
@@ -401,7 +402,7 @@ static unsigned int get_mocs_settings(struct xe_device *xe,
 		info->size = ARRAY_SIZE(dg2_mocs_desc);
 		info->table = dg2_mocs_desc;
 		info->uc_index = 1;
-		info->n_entries = XELP_NUM_MOCS_ENTRIES;
+		info->n_entries = XEHP_NUM_MOCS_ENTRIES;
 		info->unused_entries_index = 3;
 		break;
 	case XE_DG1:
-- 
2.43.0