✓ CI.checkpatch: success for series starting with [1/3] drm/xe: Fix display runtime_pm handling

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/xe: Fix display runtime_pm handling
URL   : https://patchwork.freedesktop.org/series/130450/
State : success

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
9ab59fc4b7cb7663906ac4471a262434aef57f03
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit aa42aea3a24ff0749396793d413c4f46d39d5dcf
Author: Rodrigo Vivi <rodrigo.vivi at intel.com>
Date:   Tue Feb 27 13:37:25 2024 -0500

    drm/xe: Prepare display for D3Cold
    
    Prepare power-well and DC handling for a full power
    lost during D3Cold, then sanitize it upon D3->D0.
    Otherwise we get a bunch of state mismatch.
    
    Ideally we could leave DC9 enabled and wouldn't need
    to move DC9->DC0 on every runtime resume, however,
    the disable_DC is part of the power-well checks and
    intrinsic to the dc_off power well. In the future that
    can be detangled so we can have even bigger power savings.
    But for now, let's focus on getting a D3Cold, which saves
    much more power by itself.
    
    v2: We cannot do the full-suspend-resume path or we end
    with a deadlock between xe_gem_fault and the modeset-ioctl.
    Reduce only to the power-well & DC sanitization.
    
    Cc: Anshuman Gupta <anshuman.gupta at intel.com>
    Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
+ /mt/dim checkpatch 0d7a78693be62a8d1cd311376815b89b18de8204 drm-intel
5c6deaffa01c drm/xe: Fix display runtime_pm handling
8e7dfaba2e2e drm/xe: Create a xe_pm_runtime_resume_and_get variant for display
aa42aea3a24f drm/xe: Prepare display for D3Cold