[PATCH] drm/xe/xe2: Use XE_CACHE_WB pat index
Himal Prasad Ghimiray
himal.prasad.ghimiray at intel.com
Tue Jan 2 11:33:40 UTC 2024
Use XE_CACHE_WB pat index by default on xe2 platforms and use
XE_CACHE_NONE_COMPRESSION pat index only if buffer supports
compression and indirect access of flat ccs.
Fixes the broken "xe_migrate_test kunit test" on LNL.
Cc: Thomas Hellström <thomas.hellstrom at linux.intel.com>
Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray at intel.com>
---
drivers/gpu/drm/xe/xe_migrate.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
index adf1dab5eba2..cb66636bfa6f 100644
--- a/drivers/gpu/drm/xe/xe_migrate.c
+++ b/drivers/gpu/drm/xe/xe_migrate.c
@@ -439,7 +439,7 @@ static void emit_pte(struct xe_migrate *m,
/* Indirect access needs compression enabled uncached PAT index */
if (GRAPHICS_VERx100(xe) >= 2000)
pat_index = is_comp_pte ? xe->pat.idx[XE_CACHE_NONE_COMPRESSION] :
- xe->pat.idx[XE_CACHE_NONE];
+ xe->pat.idx[XE_CACHE_WB];
else
pat_index = xe->pat.idx[XE_CACHE_WB];
@@ -729,14 +729,14 @@ struct dma_fence *xe_migrate_copy(struct xe_migrate *m,
}
if (!src_is_vram)
- emit_pte(m, bb, src_L0_pt, src_is_vram, true, &src_it, src_L0,
- src_bo);
+ emit_pte(m, bb, src_L0_pt, src_is_vram, copy_system_ccs ? true : false,
+ &src_it, src_L0, src_bo);
else
xe_res_next(&src_it, src_L0);
if (!dst_is_vram)
- emit_pte(m, bb, dst_L0_pt, dst_is_vram, true, &dst_it, src_L0,
- dst_bo);
+ emit_pte(m, bb, dst_L0_pt, dst_is_vram, copy_system_ccs ? true : false,
+ &dst_it, src_L0, dst_bo);
else
xe_res_next(&dst_it, src_L0);
@@ -978,8 +978,8 @@ struct dma_fence *xe_migrate_clear(struct xe_migrate *m,
size -= clear_L0;
/* Preemption is enabled again by the ring ops. */
if (!clear_vram) {
- emit_pte(m, bb, clear_L0_pt, clear_vram, true, &src_it, clear_L0,
- bo);
+ emit_pte(m, bb, clear_L0_pt, clear_vram, clear_system_ccs ? true : false,
+ &src_it, clear_L0, bo);
} else {
xe_res_next(&src_it, clear_L0);
}
--
2.25.1
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