[PATCH v2] drm/xe/xe2: synchronise CS_CHICKEN1 with WMTP support

[Matt Roper]

On Wed, Jan 03, 2024 at 02:05:17PM +0100, Nirmoy Das wrote:
> Recommendation is to read FUSE4 register to check if WMTP has been
> enabled/disabled by HW. If enabled we don't need to do anything special,
> however if disabled recommendation is to also disable the WMTP mode in
> the FF_SLICE_CS_CHICKEN2 register, falling back to thread-group and
> mid-batch preemption only. However on Linux, the per-context CS_CHICKEN1
> is how userspace controls pre-emption, so instead use the default lrc to
> disable WMPT using CS_CHICKEN1, if disabled by HW. Userspace is still

s/WMPT/WMTP/

> free to set CS_CHICKEN1 to whatever they want later.
> 
> v2: remove redundant version check and also add descriptive name(Matt)
> 
> Cc: Matt Roper <matthew.d.roper at intel.com>
> Co-developed-by: Matthew Auld <matthew.auld at intel.com>
> Signed-off-by: Matthew Auld <matthew.auld at intel.com>
> Signed-off-by: Nirmoy Das <nirmoy.das at intel.com>
> ---
>  drivers/gpu/drm/xe/regs/xe_gt_regs.h |  1 +
>  drivers/gpu/drm/xe/xe_hw_engine.c    | 28 ++++++++++++++++++++++++++++
>  2 files changed, 29 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index 6aaaf1f63c72..6dfad86aaea6 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -146,6 +146,7 @@
>  
>  /* Fuse readout registers for GT */
>  #define XEHP_FUSE4				XE_REG(0x9114)
> +#define   CFEG_WMTP_DISABLE			REG_BIT(20)
>  #define   CCS_EN_MASK				REG_GENMASK(19, 16)
>  #define   GT_L3_EXC_MASK			REG_GENMASK(6, 4)
>  
> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
> index 832989c83a25..88dcb8cc8beb 100644
> --- a/drivers/gpu/drm/xe/xe_hw_engine.c
> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
> @@ -316,6 +316,26 @@ static bool xe_hw_engine_match_fixed_cslice_mode(const struct xe_gt *gt,
>  	       xe_rtp_match_first_render_or_compute(gt, hwe);
>  }
>  
> +static bool xe_rtp_cfeg_wmtp_disabled(const struct xe_gt *gt,
> +				      const struct xe_hw_engine *hwe)
> +{
> +
> +	bool mtp_disabled;
> +
> +	if (GRAPHICS_VER(gt_to_xe(gt)) < 20)
> +		return false;
> +
> +	if (hwe->class != XE_ENGINE_CLASS_COMPUTE &&
> +	    hwe->class != XE_ENGINE_CLASS_RENDER)
> +		return false;
> +
> +	mtp_disabled = REG_FIELD_GET(CFEG_WMTP_DISABLE,
> +				     xe_mmio_read32(hwe->gt,
> +						    XEHP_FUSE4));

Since this is just a single bit rather than a field, it's probably
simpler to just do 

        return xe_mmio_read32(hwe->gt, XEHP_FUSE4) & CFEG_WMTP_DISABLE;

instead of the REG_FIELD_GET.

Aside from that,

Reviewed-by: Matt Roper <matthew.d.roper at intel.com>

> +	return mtp_disabled;
> +
> +}
> +
>  void
>  xe_hw_engine_setup_default_lrc_state(struct xe_hw_engine *hwe)
>  {
> @@ -346,6 +366,14 @@ xe_hw_engine_setup_default_lrc_state(struct xe_hw_engine *hwe)
>  		  XE_RTP_ACTIONS(FIELD_SET(RCU_MODE, RCU_MODE_FIXED_SLICE_CCS_MODE,
>  					   RCU_MODE_FIXED_SLICE_CCS_MODE))
>  		},
> +		/* Disable WMTP if HW doesn't support it */
> +		{ XE_RTP_NAME("DISABLE_WMTP_ON_UNSUPPORTED_HW"),
> +		  XE_RTP_RULES(FUNC(xe_rtp_cfeg_wmtp_disabled)),
> +		  XE_RTP_ACTIONS(FIELD_SET(CS_CHICKEN1(0),
> +					   PREEMPT_GPGPU_LEVEL_MASK,
> +					   PREEMPT_GPGPU_THREAD_GROUP_LEVEL)),
> +		  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE)
> +		},
>  		{}
>  	};
>  
> -- 
> 2.42.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation