✓ CI.checkpatch: success for drm/xe/migrate: Cap PTEs written by MI_STORE_DATA_IMM to 510

[Patchwork]

== Series Details ==

Series: drm/xe/migrate: Cap PTEs written by MI_STORE_DATA_IMM to 510
URL   : https://patchwork.freedesktop.org/series/128694/
State : success

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
faa12d3432d7ef7793d934cd9338c555e95a5aad
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit dbdf749ec8ccecfeb9609489866f99d6b61d3eea
Author: Matt Roper <matthew.d.roper at intel.com>
Date:   Thu Jan 11 14:02:38 2024 -0800

    drm/xe/migrate: Cap PTEs written by MI_STORE_DATA_IMM to 510
    
    Although MI_STORE_DATA_IMM's "length" field is 10-bits, 0x3FE is
    considered the largest legal value accepted.  Since that instruction
    field is always encoded in (val-2) format, this translates to 0x400
    dwords for the true maximum length of the instruction.  Subtracting the
    instruction header (1 dword) and address (2 dwords), that leaves 0x3FD
    dwords (i.e., 0x1FE qwords) for PTE values.
    
    Bspec: 60246, 45753
    Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
+ /mt/dim checkpatch 3095fbb4deb0722d417b6a4ad4213e2ed9ecd052 drm-intel
dbdf749ec drm/xe/migrate: Cap PTEs written by MI_STORE_DATA_IMM to 510