✓ CI.checkpatch: success for drm/xe/xe2: Use XE_CACHE_WB pat index (rev3)

[Patchwork]

== Series Details ==

Series: drm/xe/xe2: Use XE_CACHE_WB pat index (rev3)
URL   : https://patchwork.freedesktop.org/series/128110/
State : success

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
faa12d3432d7ef7793d934cd9338c555e95a5aad
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 5e27e3007b9316f82f19057345eed9e8f9bbfc28
Author: Himal Prasad Ghimiray <himal.prasad.ghimiray at intel.com>
Date:   Tue Jan 16 17:35:12 2024 +0530

    drm/xe/xe2: Use XE_CACHE_WB pat index
    
    The pat table entry associated with XE_CACHE_WB is coherent whereas
    XE_CACHE_NONE is non coherent. Use the coherent entry XE_CACHE_WB for
    buffers not supporting compression. For read/write to flat ccs region
    the issue is not related to coherency with cpu. The hardware expects
    the pat index associated with GPUVA for indirect access to be
    compression enabled hence use XE_CACHE_NONE_COMPRESSION.
    
    Fixes the broken "xe_migrate_test kunit test" on LNL.
    
    v2
    - Fix the argument to emit_pte, pass the bool directly. (Thomas)
    
    v3
    - Rebase
    - Update commit message (Matt)
    
    Cc: Matt Roper <matthew.d.roper at intel.com>
    Cc: Thomas Hellström <thomas.hellstrom at linux.intel.com>
    Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray at intel.com>
+ /mt/dim checkpatch 3a1d727c0061b96ddf8e653130f94ab331e2f065 drm-intel
5e27e3007 drm/xe/xe2: Use XE_CACHE_WB pat index