[PATCH] drm/xe/irq: allocate all possible msix interrupts

Jani Nikula jani.nikula at linux.intel.com
Tue Jan 16 14:25:58 UTC 2024


On Tue, 16 Jan 2024, Ohad Sharabi <osharabi at habana.ai> wrote:
> On 16/01/2024 15:07, Dani Liberman wrote:
>
> For future platforms which will support msix, need to allocate all
> possible interrupts.
>
> Signed-off-by: Dani Liberman <dliberman at habana.ai><mailto:dliberman at habana.ai>
>
> Reviewed-by: Ohad Sharabi <osharabi@<mailto:gustavo.sousa at intel.com>habana.ai>

Please use plain text when replying on the public lists.

Thanks,
Jani.

>
>
> Cc: Ohad Sharabi <osharabi at habana.ai><mailto:osharabi at habana.ai>
> ---
>  drivers/gpu/drm/xe/xe_irq.c | 15 +++++++++++++--
>  1 file changed, 13 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
> index 907c8ff0fa21..62722809a01d 100644
> --- a/drivers/gpu/drm/xe/xe_irq.c
> +++ b/drivers/gpu/drm/xe/xe_irq.c
> @@ -662,7 +662,7 @@ int xe_irq_install(struct xe_device *xe)
>  {
>         struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
>         irq_handler_t irq_handler;
> -       int err, irq;
> +       int err, irq, nvec;
>
>         irq_handler = xe_irq_handler(xe);
>         if (!irq_handler) {
> @@ -672,7 +672,18 @@ int xe_irq_install(struct xe_device *xe)
>
>         xe_irq_reset(xe);
>
> -       err = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI | PCI_IRQ_MSIX);
> +       if (pdev->msix_cap) {
> +               nvec = pci_msix_vec_count(pdev);
> +               if (nvec <= 0) {
> +                       drm_err(&xe->drm, "MSIX: Failed getting count\n");
> +                       return -EINVAL;
> +               }
> +       } else {
> +               /* device supports only msi */
> +               nvec = 1;
> +       }
> +
> +       err = pci_alloc_irq_vectors(pdev, nvec, nvec, PCI_IRQ_MSI | PCI_IRQ_MSIX);
>         if (err < 0) {
>                 drm_err(&xe->drm, "MSI/MSIX: Failed to enable support %d\n", err);
>                 return err;
>
>

-- 
Jani Nikula, Intel


More information about the Intel-xe mailing list