[PATCH v2 1/1] drm/xe: correct the calculation of remaining size

[Matt Roper]

On Tue, Jan 16, 2024 at 01:59:22PM -0800, Yang, Fei wrote:
> > On Tue, Jan 16, 2024 at 12:04:24PM -0800, fei.yang at intel.com wrote:
> >> From: Fei Yang <fei.yang at intel.com>
> >>
> >> In function write_pgtable, the calculation of chunk in the do-while
> >> loop is wrong, we should always compare against remaining size instead
> >> of the total size update->qwords.
> >> Also, when performing dword writes, dword length can be any value from
> >> 2 to 3fe, always adding 1 is wrong.
> >
> > Always adding 1 should be correct.  This field holds the number of dwords
> > for the instruction as a whole (encoded in n-2 format as it is for all GPU
> > instructions), not the number of dwords being stored by the command.  The
> > instruction always includes three initial dwords (1 for the instruction header,
> > 2 for the target address).  So if you want to store n dwords, the total
> > instruction length is n+3 which means the encoded field contents are n+1.
> 
> But according to the bspec, what you said only applies to qword writes (bit21 set),
> not dword writes. So, MI_SDI_NUM_QW looks correct, MI_SDI_NUM_DW is not.
> Am I misunderstanding?

The bspec's note about dword mode is saying that the 9:0 *field* value
can be anything from 2 up to max (aka 0x3FE).  It's making the
assumption that the reader knows that the "dword length" field of all
GPU instructions is always encoded in n-2 format.  So the number of
values that this instruction can store in dword mode is actually
1..0x3FD.


Matt

> 
> >
> >Matt
> >
> >>
> >> Signed-off-by: Fei Yang <fei.yang at intel.com>
> >> ---
> >>  drivers/gpu/drm/xe/instructions/xe_mi_commands.h | 2 +-
> >>  drivers/gpu/drm/xe/xe_migrate.c                  | 2 +-
> >>  2 files changed, 2 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/xe/instructions/xe_mi_commands.h
> >> b/drivers/gpu/drm/xe/instructions/xe_mi_commands.h
> >> index c74ceb550dce..415609b070fb 100644
> >> --- a/drivers/gpu/drm/xe/instructions/xe_mi_commands.h
> >> +++ b/drivers/gpu/drm/xe/instructions/xe_mi_commands.h
> >> @@ -36,7 +36,7 @@
> >>  #define MI_STORE_DATA_IMM           __MI_INSTR(0x20)
> >>  #define   MI_SDI_GGTT                       REG_BIT(22)
> >>  #define   MI_SDI_LEN_DW                     GENMASK(9, 0)
> >> -#define   MI_SDI_NUM_DW(x)          REG_FIELD_PREP(MI_SDI_LEN_DW, (x) + 3 - 2)
> >> +#define   MI_SDI_NUM_DW(x)          REG_FIELD_PREP(MI_SDI_LEN_DW, ((x) > 1) ? (x) : 2)
> >>  #define   MI_SDI_NUM_QW(x)          (REG_FIELD_PREP(MI_SDI_LEN_DW, 2 * (x) + 3 - 2) | \
> >>                                       REG_BIT(21))
> >>
> >> diff --git a/drivers/gpu/drm/xe/xe_migrate.c
> >> b/drivers/gpu/drm/xe/xe_migrate.c index 44725f978f3e..d5392cbbdb49
> >> 100644
> >> --- a/drivers/gpu/drm/xe/xe_migrate.c
> >> +++ b/drivers/gpu/drm/xe/xe_migrate.c
> >> @@ -1116,7 +1116,7 @@ static void write_pgtable(struct xe_tile *tile, struct xe_bb *bb, u64 ppgtt_ofs,
> >>      do {
> >>              u64 addr = ppgtt_ofs + ofs * 8;
> >>
> >> -            chunk = min(update->qwords, MAX_PTE_PER_SDI);
> >> +            chunk = min(size, MAX_PTE_PER_SDI);
> >>
> >>              /* Ensure populatefn can do memset64 by aligning bb->cs */
> >>              if (!(bb->len & 1))
> >> --
> >> 2.25.1
> >>
> >
> > --
> > Matt Roper
> > Graphics Software Engineer
> > Linux GPU Platform Enablement
> > Intel Corporation

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation