✗ CI.checkpatch: warning for drm/xe/xe2: Use XE_CACHE_WB pat index (rev4)
Patchwork
patchwork at emeril.freedesktop.org
Fri Jan 19 04:10:11 UTC 2024
== Series Details ==
Series: drm/xe/xe2: Use XE_CACHE_WB pat index (rev4)
URL : https://patchwork.freedesktop.org/series/128110/
State : warning
== Summary ==
+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
e7f730565356938dd6c63cd498218fdc5d6a22b0
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 966acc798c0fb926c0fe030236ecb5ccd2b386d8
Author: Himal Prasad Ghimiray <himal.prasad.ghimiray at intel.com>
Date: Fri Jan 19 09:48:26 2024 +0530
drm/xe/xe2: Use XE_CACHE_WB pat index
The pat table entry associated with XE_CACHE_WB is coherent whereas
XE_CACHE_NONE is non coherent. Migration expects the coherency
with cpu therefore use the coherent entry XE_CACHE_WB for
buffers not supporting compression. For read/write to flat ccs region
the issue is not related to coherency with cpu. The hardware expects
the pat index associated with GPUVA for indirect access to be
compression enabled hence use XE_CACHE_NONE_COMPRESSION.
v2
- Fix the argument to emit_pte, pass the bool directly. (Thomas)
v3
- Rebase
- Update commit message (Matt)
v4
- Add a Fixes: tag. (Thomas)
Cc: Matt Roper <matthew.d.roper at intel.com>
Cc: Thomas Hellström <thomas.hellstrom at linux.intel.com>
Fixes: 65ef8dbad1db ("drm/xe/xe2: Update emit_pte to use compression enabled PAT index")
Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray at intel.com>
+ /mt/dim checkpatch ffd89994d2da0d477d1d8a1376127b0f55338d59 drm-intel
966acc798 drm/xe/xe2: Use XE_CACHE_WB pat index
-:29: WARNING:UNKNOWN_COMMIT_ID: Unknown commit id '65ef8dbad1db', maybe rebased or not pulled?
#29:
Fixes: 65ef8dbad1db ("drm/xe/xe2: Update emit_pte to use compression enabled PAT index")
total: 0 errors, 1 warnings, 0 checks, 36 lines checked
More information about the Intel-xe
mailing list