[PATCH v4] drm/xe/xe2: Use XE_CACHE_WB pat index

[Thomas Hellström]

On 1/19/24 05:18, Himal Prasad Ghimiray wrote:
> The pat table entry associated with XE_CACHE_WB is coherent whereas
> XE_CACHE_NONE is non coherent. Migration expects the coherency
> with cpu therefore use the coherent entry XE_CACHE_WB for
> buffers not supporting compression. For read/write to flat ccs region
> the issue is not related to coherency with cpu. The hardware expects
> the pat index associated with GPUVA for indirect access to be
> compression enabled hence use XE_CACHE_NONE_COMPRESSION.
>
> v2
> - Fix the argument to emit_pte, pass the bool directly. (Thomas)
>
> v3
> - Rebase
> - Update commit message (Matt)
>
> v4
> - Add a Fixes: tag. (Thomas)
>
> Cc: Matt Roper <matthew.d.roper at intel.com>
> Cc: Thomas Hellström <thomas.hellstrom at linux.intel.com>
> Fixes: 65ef8dbad1db ("drm/xe/xe2: Update emit_pte to use compression enabled PAT index")
> Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray at intel.com>

Reviewed-by: Thomas Hellström <thomas.hellstrom at linux.intel.com>


> ---
>   drivers/gpu/drm/xe/xe_migrate.c | 14 +++++++-------
>   1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
> index 44725f978f3e..5de8ee4245c3 100644
> --- a/drivers/gpu/drm/xe/xe_migrate.c
> +++ b/drivers/gpu/drm/xe/xe_migrate.c
> @@ -481,7 +481,7 @@ static void emit_pte(struct xe_migrate *m,
>   	/* Indirect access needs compression enabled uncached PAT index */
>   	if (GRAPHICS_VERx100(xe) >= 2000)
>   		pat_index = is_comp_pte ? xe->pat.idx[XE_CACHE_NONE_COMPRESSION] :
> -					  xe->pat.idx[XE_CACHE_NONE];
> +					  xe->pat.idx[XE_CACHE_WB];
>   	else
>   		pat_index = xe->pat.idx[XE_CACHE_WB];
>   
> @@ -769,14 +769,14 @@ struct dma_fence *xe_migrate_copy(struct xe_migrate *m,
>   		if (src_is_vram && xe_migrate_allow_identity(src_L0, &src_it))
>   			xe_res_next(&src_it, src_L0);
>   		else
> -			emit_pte(m, bb, src_L0_pt, src_is_vram, true, &src_it, src_L0,
> -				 src);
> +			emit_pte(m, bb, src_L0_pt, src_is_vram, copy_system_ccs,
> +				 &src_it, src_L0, src);
>   
>   		if (dst_is_vram && xe_migrate_allow_identity(src_L0, &dst_it))
>   			xe_res_next(&dst_it, src_L0);
>   		else
> -			emit_pte(m, bb, dst_L0_pt, dst_is_vram, true, &dst_it, src_L0,
> -				 dst);
> +			emit_pte(m, bb, dst_L0_pt, dst_is_vram, copy_system_ccs,
> +				 &dst_it, src_L0, dst);
>   
>   		if (copy_system_ccs)
>   			emit_pte(m, bb, ccs_pt, false, false, &ccs_it, ccs_size, src);
> @@ -1018,8 +1018,8 @@ struct dma_fence *xe_migrate_clear(struct xe_migrate *m,
>   		if (clear_vram && xe_migrate_allow_identity(clear_L0, &src_it))
>   			xe_res_next(&src_it, clear_L0);
>   		else
> -			emit_pte(m, bb, clear_L0_pt, clear_vram, true, &src_it, clear_L0,
> -				 dst);
> +			emit_pte(m, bb, clear_L0_pt, clear_vram, clear_system_ccs,
> +				 &src_it, clear_L0, dst);
>   
>   		bb->cs[bb->len++] = MI_BATCH_BUFFER_END;
>   		update_idx = bb->len;