[PATCH 8/9] drm/xe: Print registers spread in 2 u32 as u64

Rodrigo Vivi rodrigo.vivi at intel.com
Mon Jan 22 20:14:55 UTC 2024


On Mon, Jan 22, 2024 at 09:04:44AM -0800, José Roberto de Souza wrote:
> This makes easier to use those registers when copying its values to
> calculator also makes easier for tools to parse it.
> 
> To avoids padding holes in xe_hw_engine_snapshot the u64 variables
> were moved to the top of xe_hw_engine_snapshot.reg.
> 
> Cc: Rodrigo Vivi <rodrigo.vivi at intel.com>
> Cc: Maarten Lankhorst <dev at lankhorst.se>
> Signed-off-by: José Roberto de Souza <jose.souza at intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi at intel.com>

> ---
>  drivers/gpu/drm/xe/xe_hw_engine.c       | 69 ++++++++++++-------------
>  drivers/gpu/drm/xe/xe_hw_engine_types.h | 30 ++++-------
>  2 files changed, 42 insertions(+), 57 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
> index 3aaab507f37fe..9fc30ecec0a26 100644
> --- a/drivers/gpu/drm/xe/xe_hw_engine.c
> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
> @@ -749,6 +749,7 @@ struct xe_hw_engine_snapshot *
>  xe_hw_engine_snapshot_capture(struct xe_hw_engine *hwe)
>  {
>  	struct xe_hw_engine_snapshot *snapshot;
> +	u64 val;
>  
>  	if (!xe_hw_engine_is_valid(hwe))
>  		return NULL;
> @@ -766,19 +767,31 @@ xe_hw_engine_snapshot_capture(struct xe_hw_engine *hwe)
>  						    hwe->domain);
>  	snapshot->mmio_base = hwe->mmio_base;
>  
> -	snapshot->reg.ring_hwstam = hw_engine_mmio_read32(hwe, RING_HWSTAM(0));
> -	snapshot->reg.ring_hws_pga = hw_engine_mmio_read32(hwe,
> -							   RING_HWS_PGA(0));
> -	snapshot->reg.ring_execlist_status_lo =
> +	snapshot->reg.ring_execlist_status =
>  		hw_engine_mmio_read32(hwe, RING_EXECLIST_STATUS_LO(0));
> -	snapshot->reg.ring_execlist_status_hi =
> -		hw_engine_mmio_read32(hwe, RING_EXECLIST_STATUS_HI(0));
> -	snapshot->reg.ring_execlist_sq_contents_lo =
> -		hw_engine_mmio_read32(hwe,
> -				      RING_EXECLIST_SQ_CONTENTS_LO(0));
> -	snapshot->reg.ring_execlist_sq_contents_hi =
> -		hw_engine_mmio_read32(hwe,
> -				      RING_EXECLIST_SQ_CONTENTS_HI(0));
> +	val = hw_engine_mmio_read32(hwe, RING_EXECLIST_STATUS_HI(0));
> +	snapshot->reg.ring_execlist_status |= val << 32;
> +
> +	snapshot->reg.ring_execlist_sq_contents =
> +		hw_engine_mmio_read32(hwe, RING_EXECLIST_SQ_CONTENTS_LO(0));
> +	val = hw_engine_mmio_read32(hwe, RING_EXECLIST_SQ_CONTENTS_HI(0));
> +	snapshot->reg.ring_execlist_sq_contents |= val << 32;
> +
> +	snapshot->reg.ring_acthd = hw_engine_mmio_read32(hwe, RING_ACTHD(0));
> +	val = hw_engine_mmio_read32(hwe, RING_ACTHD_UDW(0));
> +	snapshot->reg.ring_acthd |= val << 32;
> +
> +	snapshot->reg.ring_bbaddr = hw_engine_mmio_read32(hwe, RING_BBADDR(0));
> +	val = hw_engine_mmio_read32(hwe, RING_BBADDR_UDW(0));
> +	snapshot->reg.ring_bbaddr |= val << 32;
> +
> +	snapshot->reg.ring_dma_fadd =
> +		hw_engine_mmio_read32(hwe, RING_DMA_FADD(0));
> +	val = hw_engine_mmio_read32(hwe, RING_DMA_FADD_UDW(0));
> +	snapshot->reg.ring_dma_fadd |= val << 32;
> +
> +	snapshot->reg.ring_hwstam = hw_engine_mmio_read32(hwe, RING_HWSTAM(0));
> +	snapshot->reg.ring_hws_pga = hw_engine_mmio_read32(hwe, RING_HWS_PGA(0));
>  	snapshot->reg.ring_start = hw_engine_mmio_read32(hwe, RING_START(0));
>  	snapshot->reg.ring_head =
>  		hw_engine_mmio_read32(hwe, RING_HEAD(0)) & HEAD_ADDR;
> @@ -792,16 +805,6 @@ xe_hw_engine_snapshot_capture(struct xe_hw_engine *hwe)
>  	snapshot->reg.ring_esr = hw_engine_mmio_read32(hwe, RING_ESR(0));
>  	snapshot->reg.ring_emr = hw_engine_mmio_read32(hwe, RING_EMR(0));
>  	snapshot->reg.ring_eir = hw_engine_mmio_read32(hwe, RING_EIR(0));
> -	snapshot->reg.ring_acthd_udw =
> -		hw_engine_mmio_read32(hwe, RING_ACTHD_UDW(0));
> -	snapshot->reg.ring_acthd = hw_engine_mmio_read32(hwe, RING_ACTHD(0));
> -	snapshot->reg.ring_bbaddr_udw =
> -		hw_engine_mmio_read32(hwe, RING_BBADDR_UDW(0));
> -	snapshot->reg.ring_bbaddr = hw_engine_mmio_read32(hwe, RING_BBADDR(0));
> -	snapshot->reg.ring_dma_fadd_udw =
> -		hw_engine_mmio_read32(hwe, RING_DMA_FADD_UDW(0));
> -	snapshot->reg.ring_dma_fadd =
> -		hw_engine_mmio_read32(hwe, RING_DMA_FADD(0));
>  	snapshot->reg.ipehr = hw_engine_mmio_read32(hwe, RING_IPEHR(0));
>  
>  	if (snapshot->class == XE_ENGINE_CLASS_COMPUTE)
> @@ -830,14 +833,10 @@ void xe_hw_engine_snapshot_print(struct xe_hw_engine_snapshot *snapshot,
>  		   snapshot->forcewake.domain, snapshot->forcewake.ref);
>  	drm_printf(p, "\tHWSTAM: 0x%08x\n", snapshot->reg.ring_hwstam);
>  	drm_printf(p, "\tRING_HWS_PGA: 0x%08x\n", snapshot->reg.ring_hws_pga);
> -	drm_printf(p, "\tRING_EXECLIST_STATUS_LO: 0x%08x\n",
> -		   snapshot->reg.ring_execlist_status_lo);
> -	drm_printf(p, "\tRING_EXECLIST_STATUS_HI: 0x%08x\n",
> -		   snapshot->reg.ring_execlist_status_hi);
> -	drm_printf(p, "\tRING_EXECLIST_SQ_CONTENTS_LO: 0x%08x\n",
> -		   snapshot->reg.ring_execlist_sq_contents_lo);
> -	drm_printf(p, "\tRING_EXECLIST_SQ_CONTENTS_HI: 0x%08x\n",
> -		   snapshot->reg.ring_execlist_sq_contents_hi);
> +	drm_printf(p, "\tRING_EXECLIST_STATUS: 0x%016llx\n",
> +		   snapshot->reg.ring_execlist_status);
> +	drm_printf(p, "\tRING_EXECLIST_SQ_CONTENTS: 0x%016llx\n",
> +		   snapshot->reg.ring_execlist_sq_contents);
>  	drm_printf(p, "\tRING_START: 0x%08x\n", snapshot->reg.ring_start);
>  	drm_printf(p, "\tRING_HEAD:  0x%08x\n", snapshot->reg.ring_head);
>  	drm_printf(p, "\tRING_TAIL:  0x%08x\n", snapshot->reg.ring_tail);
> @@ -849,13 +848,9 @@ void xe_hw_engine_snapshot_print(struct xe_hw_engine_snapshot *snapshot,
>  	drm_printf(p, "\tRING_ESR:   0x%08x\n", snapshot->reg.ring_esr);
>  	drm_printf(p, "\tRING_EMR:   0x%08x\n", snapshot->reg.ring_emr);
>  	drm_printf(p, "\tRING_EIR:   0x%08x\n", snapshot->reg.ring_eir);
> -	drm_printf(p, "\tACTHD:  0x%08x_%08x\n", snapshot->reg.ring_acthd_udw,
> -		   snapshot->reg.ring_acthd);
> -	drm_printf(p, "\tBBADDR: 0x%08x_%08x\n", snapshot->reg.ring_bbaddr_udw,
> -		   snapshot->reg.ring_bbaddr);
> -	drm_printf(p, "\tDMA_FADDR: 0x%08x_%08x\n",
> -		   snapshot->reg.ring_dma_fadd_udw,
> -		   snapshot->reg.ring_dma_fadd);
> +	drm_printf(p, "\tACTHD:  0x%016llx\n", snapshot->reg.ring_acthd);
> +	drm_printf(p, "\tBBADDR: 0x%016llx\n", snapshot->reg.ring_bbaddr);
> +	drm_printf(p, "\tDMA_FADDR: 0x%016llx\n", snapshot->reg.ring_dma_fadd);
>  	drm_printf(p, "\tIPEHR: 0x%08x\n\n", snapshot->reg.ipehr);
>  	if (snapshot->class == XE_ENGINE_CLASS_COMPUTE)
>  		drm_printf(p, "\tRCU_MODE: 0x%08x\n",
> diff --git a/drivers/gpu/drm/xe/xe_hw_engine_types.h b/drivers/gpu/drm/xe/xe_hw_engine_types.h
> index dfeaaac08b7f9..d55c25fbf1371 100644
> --- a/drivers/gpu/drm/xe/xe_hw_engine_types.h
> +++ b/drivers/gpu/drm/xe/xe_hw_engine_types.h
> @@ -173,18 +173,20 @@ struct xe_hw_engine_snapshot {
>  	u32 mmio_base;
>  	/** @reg: Useful MMIO register snapshot */
>  	struct {
> +		/** @ring_execlist_status: RING_EXECLIST_STATUS */
> +		u64 ring_execlist_status;
> +		/** @ring_execlist_sq_contents: RING_EXECLIST_SQ_CONTENTS */
> +		u64 ring_execlist_sq_contents;
> +		/** @ring_acthd: RING_ACTHD */
> +		u64 ring_acthd;
> +		/** @ring_bbaddr: RING_BBADDR */
> +		u64 ring_bbaddr;
> +		/** @ring_dma_fadd: RING_DMA_FADD */
> +		u64 ring_dma_fadd;
>  		/** @ring_hwstam: RING_HWSTAM */
>  		u32 ring_hwstam;
>  		/** @ring_hws_pga: RING_HWS_PGA */
>  		u32 ring_hws_pga;
> -		/** @ring_execlist_status_lo: RING_EXECLIST_STATUS_LO */
> -		u32 ring_execlist_status_lo;
> -		/** @ring_execlist_status_hi: RING_EXECLIST_STATUS_HI */
> -		u32 ring_execlist_status_hi;
> -		/** @ring_execlist_sq_contents_lo: RING_EXECLIST_SQ_CONTENTS */
> -		u32 ring_execlist_sq_contents_lo;
> -		/** @ring_execlist_sq_contents_hi: RING_EXECLIST_SQ_CONTENTS + 4 */
> -		u32 ring_execlist_sq_contents_hi;
>  		/** @ring_start: RING_START */
>  		u32 ring_start;
>  		/** @ring_head: RING_HEAD */
> @@ -205,18 +207,6 @@ struct xe_hw_engine_snapshot {
>  		u32 ring_emr;
>  		/** @ring_eir: RING_EIR */
>  		u32 ring_eir;
> -		/** @ring_acthd_udw: RING_ACTHD_UDW */
> -		u32 ring_acthd_udw;
> -		/** @ring_acthd: RING_ACTHD */
> -		u32 ring_acthd;
> -		/** @ring_bbaddr_udw: RING_BBADDR_UDW */
> -		u32 ring_bbaddr_udw;
> -		/** @ring_bbaddr: RING_BBADDR */
> -		u32 ring_bbaddr;
> -		/** @ring_dma_fadd_udw: RING_DMA_FADD_UDW */
> -		u32 ring_dma_fadd_udw;
> -		/** @ring_dma_fadd: RING_DMA_FADD */
> -		u32 ring_dma_fadd;
>  		/** @ipehr: IPEHR */
>  		u32 ipehr;
>  		/** @rcu_mode: RCU_MODE */
> -- 
> 2.43.0
> 


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