✓ CI.checkpatch: success for drm/xe/gsc: Handle GSCCS ER interrupt

[Patchwork]

== Series Details ==

Series: drm/xe/gsc: Handle GSCCS ER interrupt
URL   : https://patchwork.freedesktop.org/series/129182/
State : success

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
b2ca823f819193c33ab811dfac08c614138d6d46
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 8039aae8b396b4569e8fcfb638298c73f50e2b3a
Author: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>
Date:   Thu Jan 25 13:55:43 2024 -0800

    drm/xe/gsc: Handle GSCCS ER interrupt
    
    Starting on Xe2, the GSCCS engine reset is a 2-step process. When the
    driver or the GuC hit the GDRST register, the CS is immediately reset
    and a success is reported, but the GSC shim keeps resetting in the
    background. While the shim reset is ongoing, the CS is able to accept
    new context submission, but any commands that require the shim will
    be stalled until the reset is completed. This means that we can keep
    submitting to the GSCCS as long as we make sure that the preemption
    timeout is big enough to cover any delay introduced by the reset
    (which it already is).
    When the shim reset completes, a specific CS interrupt is triggered,
    in response to which we need to check the GSCI_TIMER_STATUS register
    to see if the reset was successful or not.
    Note that the GSCI_TIMER_STATUS register is not power save/restored,
    so it gets reset on MC6 entry. However, a reset failure stops MC6,
    so in that scenario we're always guaranteed to find the correct value.
    
    Since we can't check the register within interrupt context, the
    existing GSC worker has been updated to handle it.
    The expected action to take on ER failure is to trigger a driver FLR,
    but we still don't support that, so for now we just print an error. A
    comment has been added to the code to keep track of the FLR requirement.
    
    Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>
+ /mt/dim checkpatch 38a58d4231067e1b548c12ee521b73ffc0ebb73a drm-intel
8039aae8b drm/xe/gsc: Handle GSCCS ER interrupt