[PATCH 2/3] drm/xe: Kill regs/xe_sriov_regs.h

[Ghimiray, Himal Prasad]

On 03-07-2024 00:07, Michal Wajdeczko wrote:
> There is no real benefit to maintain a separate file. The register
> definitions related to SR-IOV can be placed in existing headers.
> 
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko at intel.com>
> ---
>   drivers/gpu/drm/xe/regs/xe_gt_regs.h    |  6 ++++++
>   drivers/gpu/drm/xe/regs/xe_regs.h       |  6 ++++++
>   drivers/gpu/drm/xe/regs/xe_sriov_regs.h | 23 -----------------------
>   drivers/gpu/drm/xe/xe_gt_sriov_pf.c     |  2 +-
>   drivers/gpu/drm/xe/xe_lmtt.c            |  2 +-
>   drivers/gpu/drm/xe/xe_sriov.c           |  2 +-
>   6 files changed, 15 insertions(+), 26 deletions(-)
>   delete mode 100644 drivers/gpu/drm/xe/regs/xe_sriov_regs.h
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index d44564bad009..141d0e0faa21 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -88,6 +88,8 @@
>   #define VE1_AUX_INV				XE_REG(0x42b8)
>   #define   AUX_INV				REG_BIT(0)
>   
> +#define XE2_LMEM_CFG				XE_REG(0x48b0)
> +
>   #define XEHP_TILE_ADDR_RANGE(_idx)		XE_REG_MCR(0x4900 + (_idx) * 4)
>   #define XEHP_FLAT_CCS_BASE_ADDR			XE_REG_MCR(0x4910)
>   #define XEHP_FLAT_CCS_PTR			REG_GENMASK(31, 8)
> @@ -395,6 +397,10 @@
>   #define   INVALIDATION_BROADCAST_MODE_DIS	REG_BIT(12)
>   #define   GLOBAL_INVALIDATION_MODE		REG_BIT(2)
>   
> +#define LMEM_CFG				XE_REG(0xcf58)
> +#define   LMEM_EN				REG_BIT(31)
> +#define   LMTT_DIR_PTR				REG_GENMASK(30, 0) /* in multiples of 64KB */
> +
>   #define HALF_SLICE_CHICKEN5			XE_REG_MCR(0xe188, XE_REG_OPTION_MASKED)
>   #define   DISABLE_SAMPLE_G_PERFORMANCE		REG_BIT(0)
>   
> diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe_regs.h
> index 23ecba38ed41..55bf47c99016 100644
> --- a/drivers/gpu/drm/xe/regs/xe_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_regs.h
> @@ -30,6 +30,9 @@
>   #define GU_DEBUG				XE_REG(0x101018)
>   #define   DRIVERFLR_STATUS			REG_BIT(31)
>   
> +#define VIRTUAL_CTRL_REG			XE_REG(0x10108c)
> +#define   GUEST_GTT_UPDATE_EN			REG_BIT(8)
> +
>   #define XEHP_MTCFG_ADDR				XE_REG(0x101800)
>   #define   TILE_COUNT				REG_GENMASK(15, 8)
>   
> @@ -66,6 +69,9 @@
>   #define   DISPLAY_IRQ				REG_BIT(16)
>   #define   GT_DW_IRQ(x)				REG_BIT(x)
>   
> +#define VF_CAP_REG				XE_REG(0x1901f8, XE_REG_OPTION_VF)
> +#define   VF_CAP				REG_BIT(0)
> +
>   #define PVC_RP_STATE_CAP			XE_REG(0x281014)
>   
>   #endif
> diff --git a/drivers/gpu/drm/xe/regs/xe_sriov_regs.h b/drivers/gpu/drm/xe/regs/xe_sriov_regs.h
> deleted file mode 100644
> index 017b4ddd1ecf..000000000000
> --- a/drivers/gpu/drm/xe/regs/xe_sriov_regs.h
> +++ /dev/null
> @@ -1,23 +0,0 @@
> -/* SPDX-License-Identifier: MIT */
> -/*
> - * Copyright © 2023 Intel Corporation
> - */
> -
> -#ifndef _REGS_XE_SRIOV_REGS_H_
> -#define _REGS_XE_SRIOV_REGS_H_
> -
> -#include "regs/xe_reg_defs.h"
> -
> -#define XE2_LMEM_CFG			XE_REG(0x48b0)
> -
> -#define LMEM_CFG			XE_REG(0xcf58)
> -#define   LMEM_EN			REG_BIT(31)
> -#define   LMTT_DIR_PTR			REG_GENMASK(30, 0) /* in multiples of 64KB */
> -
> -#define VIRTUAL_CTRL_REG		XE_REG(0x10108c)
> -#define   GUEST_GTT_UPDATE_EN		REG_BIT(8)
> -
> -#define VF_CAP_REG			XE_REG(0x1901f8, XE_REG_OPTION_VF)
> -#define   VF_CAP			REG_BIT(0)
> -
> -#endif
> diff --git a/drivers/gpu/drm/xe/xe_gt_sriov_pf.c b/drivers/gpu/drm/xe/xe_gt_sriov_pf.c
> index 9dbba9ab7a9a..ef239440963c 100644
> --- a/drivers/gpu/drm/xe/xe_gt_sriov_pf.c
> +++ b/drivers/gpu/drm/xe/xe_gt_sriov_pf.c
> @@ -5,7 +5,7 @@
>   
>   #include <drm/drm_managed.h>
>   
> -#include "regs/xe_sriov_regs.h"
> +#include "regs/xe_regs.h"
>   
>   #include "xe_gt_sriov_pf.h"
>   #include "xe_gt_sriov_pf_config.h"
> diff --git a/drivers/gpu/drm/xe/xe_lmtt.c b/drivers/gpu/drm/xe/xe_lmtt.c
> index 418661a88918..c5fdb36b6d33 100644
> --- a/drivers/gpu/drm/xe/xe_lmtt.c
> +++ b/drivers/gpu/drm/xe/xe_lmtt.c
> @@ -7,7 +7,7 @@
>   
>   #include <drm/drm_managed.h>
>   
> -#include "regs/xe_sriov_regs.h"
> +#include "regs/xe_gt_regs.h"
>   
>   #include "xe_assert.h"
>   #include "xe_bo.h"
> diff --git a/drivers/gpu/drm/xe/xe_sriov.c b/drivers/gpu/drm/xe/xe_sriov.c
> index a274a5fb1401..5a1d65e4f19f 100644
> --- a/drivers/gpu/drm/xe/xe_sriov.c
> +++ b/drivers/gpu/drm/xe/xe_sriov.c
> @@ -5,7 +5,7 @@
>   
>   #include <drm/drm_managed.h>
>   
> -#include "regs/xe_sriov_regs.h"
> +#include "regs/xe_regs.h"

LGTM
Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray at intel.com>

>   
>   #include "xe_assert.h"
>   #include "xe_device.h"