[PATCH] drm/xe: Simplify selecting caching mode

[Matthew Brost]

On Mon, Jul 08, 2024 at 02:05:50PM +0200, Maarten Lankhorst wrote:
> The switch is slightly overkill, with the default already set to cached
> since previous commit.
> 
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com>

Good cleanup.

Reviewed-by: Matthew Brost <matthew.brost at intel.com>

> ---
>  drivers/gpu/drm/xe/xe_bo.c | 12 ++----------
>  1 file changed, 2 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_bo.c b/drivers/gpu/drm/xe/xe_bo.c
> index 31192d983d9e..d3511dd4a488 100644
> --- a/drivers/gpu/drm/xe/xe_bo.c
> +++ b/drivers/gpu/drm/xe/xe_bo.c
> @@ -364,15 +364,6 @@ static struct ttm_tt *xe_ttm_tt_create(struct ttm_buffer_object *ttm_bo,
>  	 * CPU.
>  	 */
>  	if (!IS_DGFX(xe)) {
> -		switch (bo->cpu_caching) {
> -		case DRM_XE_GEM_CPU_CACHING_WC:
> -			caching = ttm_write_combined;
> -			break;
> -		default:
> -			caching = ttm_cached;
> -			break;
> -		}
> -
>  		WARN_ON((bo->flags & XE_BO_FLAG_USER) && !bo->cpu_caching);
>  
>  		/*
> @@ -381,7 +372,8 @@ static struct ttm_tt *xe_ttm_tt_create(struct ttm_buffer_object *ttm_bo,
>  		 * For Xe_LPG and beyond, PPGTT PTE lookups are also
>  		 * non-coherent and require a CPU:WC mapping.
>  		 */
> -		if ((!bo->cpu_caching && bo->flags & XE_BO_FLAG_SCANOUT) ||
> +		if (bo->cpu_caching == DRM_XE_GEM_CPU_CACHING_WC ||
> +		    (!bo->cpu_caching && bo->flags & XE_BO_FLAG_SCANOUT) ||
>  		    (xe->info.graphics_verx100 >= 1270 &&
>  		     bo->flags & XE_BO_FLAG_PAGETABLE))
>  			caching = ttm_write_combined;
> -- 
> 2.45.2
>