✓ CI.checkpatch: success for drm/xe/uapi: Expose EU width via topology query

Patchwork patchwork at emeril.freedesktop.org
Wed Jul 10 06:20:05 UTC 2024


== Series Details ==

Series: drm/xe/uapi: Expose EU width via topology query
URL   : https://patchwork.freedesktop.org/series/135926/
State : success

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
51ce9f6cd981d42d7467409d7dbc559a450abc1e
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 0a546f345160fbab444a37d9ba666b865f7cf341
Author: Lucas De Marchi <lucas.demarchi at intel.com>
Date:   Tue Jul 9 22:53:54 2024 -0700

    drm/xe/uapi: Expose EU width via topology query
    
    PVC, Xe2 and later platforms have a 16 wide EU. We were implicitly
    reporting for PVC the number of 16-wide EUs without giving userspace any
    hint that they were different than for other platforms. Xe2 and later
    also have 16-wide, but in those case the reported number would
    correspond to the 8-wide count.
    
    Add a new item to the topology that aims to clarify what the EU_PER_DSS
    mask means. This new item uses mask[] as a single u8 value. Xe2 and
    later platforms start returning the number of SIMD16 EUs.
    
    Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
+ /mt/dim checkpatch 1c05c3d64de33058a86fa2c4ebb54d7c8bda573a drm-intel
0a546f345160 drm/xe/uapi: Expose EU width via topology query




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