[PATCH] drm/xe: Refactor mmio setup for multi-tile

Lucas De Marchi lucas.demarchi at intel.com
Wed Jul 17 19:29:08 UTC 2024


On Tue, Jul 16, 2024 at 05:03:42PM GMT, Lucas De Marchi wrote:
>On Tue, Jul 16, 2024 at 11:51:05PM GMT, Michal Wajdeczko wrote:
>>
>>
>>On 16.07.2024 21:54, Lucas De Marchi wrote:
>>>Extract functions to setup the multi-tile mmio space and extension
>>>space, while better documenting the final memory layout.  No change in
>>>behavior.
>>>
>>>Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
>>>---
>>>
>>>tested only on single-tile platforms for now. It shouldn't change the
>>>behavior, but it would be good to get some extra testing.
>>
>>hmm, but CI likely wont help here as our PVC are running with:
>>
>><6>[  149.783555] xe 0000:aa:00.0: [drm] tile_count: 2, reduced_tile_count 1
>
>yes... I will have to do some manual testing and also asking for help
>from original authors (Cc'ed) to check if it doesn't break their use
>case.

just tested here on a 2T PVC and it seems to work as well as before.

Lucas De Marchi


More information about the Intel-xe mailing list