[PATCH] drm/xe/gt: Apply Wa_14020881953

[Vinay Belgaumkar]

This WA requires us to disable Render power gating. There is a second part
to the WA which requires setting a WA bit in GuC. That will be done once
GuC FW has those changes.

Cc: Matt Roper <matthew.d.roper at intel.com>
Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar at intel.com>
---
 drivers/gpu/drm/xe/xe_gt_idle.c    | 7 ++++++-
 drivers/gpu/drm/xe/xe_wa_oob.rules | 1 +
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/xe_gt_idle.c b/drivers/gpu/drm/xe/xe_gt_idle.c
index 67aba4140510..3ed60a212ff6 100644
--- a/drivers/gpu/drm/xe/xe_gt_idle.c
+++ b/drivers/gpu/drm/xe/xe_gt_idle.c
@@ -4,6 +4,7 @@
  */
 
 #include <drm/drm_managed.h>
+#include <generated/xe_wa_oob.h>
 
 #include "xe_force_wake.h"
 #include "xe_device.h"
@@ -16,6 +17,7 @@
 #include "xe_mmio.h"
 #include "xe_pm.h"
 #include "xe_sriov.h"
+#include "xe_wa.h"
 
 /**
  * DOC: Xe GT Idle
@@ -110,7 +112,10 @@ void xe_gt_idle_enable_pg(struct xe_gt *gt)
 
 	xe_device_assert_mem_access(gt_to_xe(gt));
 
-	pg_enable = RENDER_POWERGATE_ENABLE | MEDIA_POWERGATE_ENABLE;
+	if (XE_WA(gt, 14020881953))
+		pg_enable = MEDIA_POWERGATE_ENABLE;
+	else
+		pg_enable = RENDER_POWERGATE_ENABLE | MEDIA_POWERGATE_ENABLE;
 
 	for (i = XE_HW_ENGINE_VCS0, j = 0; i <= XE_HW_ENGINE_VCS7; ++i, ++j) {
 		if ((gt->info.engine_mask & BIT(i)))
diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
index 540d38603f32..c513b801655c 100644
--- a/drivers/gpu/drm/xe/xe_wa_oob.rules
+++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
@@ -31,3 +31,4 @@
 		GRAPHICS_VERSION(2001)
 22019338487_display	PLATFORM(LUNARLAKE)
 16023588340	GRAPHICS_VERSION(2001)
+14020881953	GRAPHICS_VERSION_RANGE(2001, 2004)
-- 
2.38.1