[PATCH v3 2/2] drm/xe: flush engine buffers before signalling user fence on all engines

[Cavitt, Jonathan]

-----Original Message-----
From: Intel-xe <intel-xe-bounces at lists.freedesktop.org> On Behalf Of Andrzej Hajda
Sent: Wednesday, June 5, 2024 12:30 AM
To: intel-xe at lists.freedesktop.org
Cc: Thomas Hellström <thomas.hellstrom at linux.intel.com>; Brost, Matthew <matthew.brost at intel.com>; De Marchi, Lucas <lucas.demarchi at intel.com>; Maarten Lankhorst <maarten.lankhorst at linux.intel.com>; Auld, Matthew <matthew.auld at intel.com>; Hajda, Andrzej <andrzej.hajda at intel.com>
Subject: [PATCH v3 2/2] drm/xe: flush engine buffers before signalling user fence on all engines
> 
> Tests show that user fence signalling requires kind of write barrier,
> otherwise not all writes performed by the workload will be available
> to userspace. It is already done for render and compute, we need it
> also for the rest: video, gsc, copy.

I presume the method we use to apply a write barrier to render-compute
cannot be transferred over 1-to-1 for the other engines:
Reviewed-by: Jonathan Cavitt <jonathan.cavitt at intel.com>
-Jonathan Cavitt

> 
> Fixes: dd08ebf6c352 ("drm/xe: Introduce a new DRM driver for Intel GPUs")
> Signed-off-by: Andrzej Hajda <andrzej.hajda at intel.com>
> Reviewed-by: Thomas Hellström <thomas.hellstrom at linux.intel.com>
> ---
>  drivers/gpu/drm/xe/xe_ring_ops.c | 18 ++++++++++++++++--
>  1 file changed, 16 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c
> index b11b3cd16b5e..db630d27beba 100644
> --- a/drivers/gpu/drm/xe/xe_ring_ops.c
> +++ b/drivers/gpu/drm/xe/xe_ring_ops.c
> @@ -80,6 +80,16 @@ static int emit_store_imm_ggtt(u32 addr, u32 value, u32 *dw, int i)
>  	return i;
>  }
>  
> +static int emit_flush_dw(u32 *dw, int i)
> +{
> +	dw[i++] = MI_FLUSH_DW | MI_FLUSH_IMM_DW;
> +	dw[i++] = 0;
> +	dw[i++] = 0;
> +	dw[i++] = 0;
> +
> +	return i;
> +}
> +
>  static int emit_flush_imm_ggtt(u32 addr, u32 value, bool invalidate_tlb,
>  			       u32 *dw, int i)
>  {
> @@ -234,10 +244,12 @@ static void __emit_job_gen12_simple(struct xe_sched_job *job, struct xe_lrc *lrc
>  
>  	i = emit_bb_start(batch_addr, ppgtt_flag, dw, i);
>  
> -	if (job->user_fence.used)
> +	if (job->user_fence.used) {
> +		i = emit_flush_dw(dw, i);
>  		i = emit_store_imm_ppgtt_posted(job->user_fence.addr,
>  						job->user_fence.value,
>  						dw, i);
> +	}
>  
>  	i = emit_flush_imm_ggtt(xe_lrc_seqno_ggtt_addr(lrc), seqno, false, dw, i);
>  
> @@ -293,10 +305,12 @@ static void __emit_job_gen12_video(struct xe_sched_job *job, struct xe_lrc *lrc,
>  
>  	i = emit_bb_start(batch_addr, ppgtt_flag, dw, i);
>  
> -	if (job->user_fence.used)
> +	if (job->user_fence.used) {
> +		i = emit_flush_dw(dw, i);
>  		i = emit_store_imm_ppgtt_posted(job->user_fence.addr,
>  						job->user_fence.value,
>  						dw, i);
> +	}
>  
>  	i = emit_flush_imm_ggtt(xe_lrc_seqno_ggtt_addr(lrc), seqno, false, dw, i);
>  
> 
> -- 
> 2.34.1
> 
>