[PATCH v4 6/6] drm/xe: Add reg read/write trace

[Lucas De Marchi]

On Wed, Jun 05, 2024 at 05:18:14PM GMT, Radhakrishna Sripada wrote:
>This will help debug register read/writes and provides
>a way to trace all the mmio transactions.
>
>v2: Fix kunit error
>v3: Print devid to help in multi-gpu setup
>v3: rebase and use variable sized variant to display
>    dev name(Gustavo)
>
>Cc: Gustavo Sousa <gustavo.sousa at intel.com>
>Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada at intel.com>
>---
> drivers/gpu/drm/xe/xe_mmio.c  | 24 ++++++++++++++++++++----
> drivers/gpu/drm/xe/xe_trace.h | 28 ++++++++++++++++++++++++++++
> 2 files changed, 48 insertions(+), 4 deletions(-)
>
>diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
>index 7962eeb9adb7..feba35ad6a3e 100644
>--- a/drivers/gpu/drm/xe/xe_mmio.c
>+++ b/drivers/gpu/drm/xe/xe_mmio.c
>@@ -21,6 +21,8 @@
> #include "xe_gt_sriov_vf.h"
> #include "xe_macros.h"
> #include "xe_sriov.h"
>+#include "xe_tile.h"
>+#include "xe_trace.h"
>
> static void tiles_fini(void *arg)
> {
>@@ -124,16 +126,24 @@ u8 xe_mmio_read8(struct xe_gt *gt, struct xe_reg reg)
> {
> 	struct xe_tile *tile = gt_to_tile(gt);
> 	u32 addr = xe_mmio_adjusted_addr(gt, reg.addr);
>+	u8 val;
>
>-	return readb((reg.ext ? tile->mmio_ext.regs : tile->mmio.regs) + addr);
>+	val = readb((reg.ext ? tile->mmio_ext.regs : tile->mmio.regs) + addr);
>+	trace_xe_reg_rw(gt, false, addr, val, sizeof(val));
>+
>+	return val;
> }
>
> u16 xe_mmio_read16(struct xe_gt *gt, struct xe_reg reg)
> {
> 	struct xe_tile *tile = gt_to_tile(gt);
> 	u32 addr = xe_mmio_adjusted_addr(gt, reg.addr);
>+	u16 val;
>+
>+	val = readw((reg.ext ? tile->mmio_ext.regs : tile->mmio.regs) + addr);
>+	trace_xe_reg_rw(gt, false, addr, val, sizeof(val));
>
>-	return readw((reg.ext ? tile->mmio_ext.regs : tile->mmio.regs) + addr);
>+	return val;
> }
>
> void xe_mmio_write32(struct xe_gt *gt, struct xe_reg reg, u32 val)
>@@ -141,6 +151,7 @@ void xe_mmio_write32(struct xe_gt *gt, struct xe_reg reg, u32 val)
> 	struct xe_tile *tile = gt_to_tile(gt);
> 	u32 addr = xe_mmio_adjusted_addr(gt, reg.addr);
>
>+	trace_xe_reg_rw(gt, true, addr, val, sizeof(val));
> 	writel(val, (reg.ext ? tile->mmio_ext.regs : tile->mmio.regs) + addr);
> }
>
>@@ -148,11 +159,16 @@ u32 xe_mmio_read32(struct xe_gt *gt, struct xe_reg reg)
> {
> 	struct xe_tile *tile = gt_to_tile(gt);
> 	u32 addr = xe_mmio_adjusted_addr(gt, reg.addr);
>+	u32 val;
>
> 	if (!reg.vf && IS_SRIOV_VF(gt_to_xe(gt)))
>-		return xe_gt_sriov_vf_read32(gt, reg);
>+		val = xe_gt_sriov_vf_read32(gt, reg);
>+	else
>+		val = readl((reg.ext ? tile->mmio_ext.regs : tile->mmio.regs) + addr);
>+
>+	trace_xe_reg_rw(gt, false, addr, val, sizeof(val));
>
>-	return readl((reg.ext ? tile->mmio_ext.regs : tile->mmio.regs) + addr);
>+	return val;
> }
>
> u32 xe_mmio_rmw32(struct xe_gt *gt, struct xe_reg reg, u32 clr, u32 set)
>diff --git a/drivers/gpu/drm/xe/xe_trace.h b/drivers/gpu/drm/xe/xe_trace.h
>index a22db52e88e3..be0ba5104e58 100644
>--- a/drivers/gpu/drm/xe/xe_trace.h
>+++ b/drivers/gpu/drm/xe/xe_trace.h
>@@ -347,6 +347,34 @@ DEFINE_EVENT(xe_hw_fence, xe_hw_fence_free,
> 	     TP_ARGS(fence)
> );
>
>+TRACE_EVENT(xe_reg_rw,
>+	TP_PROTO(struct xe_gt *gt, bool write, u32 reg, u64 val, int len),
>+
>+	TP_ARGS(gt, write, reg, val, len),
>+
>+	TP_STRUCT__entry(
>+		__string(dev, __dev_name_gt(gt))
>+		__field(u64, val)
>+		__field(u32, reg)
>+		__field(u16, write)
>+		__field(u16, len)
>+		),
>+
>+	TP_fast_assign(
>+		__assign_str(dev, __dev_name_gt(gt));

after commit 2c92ca849fcc6ee7d0c358e9959abc9f58661aea, __assign_str()
has only 1 param.

Lucas De Marchi