[PATCH v2 1/2] drm/xe/xe_gt_idle: use GT forcewake domain assertion

[Riana Tauro]

On 6/6/2024 11:36 AM, Ghimiray, Himal Prasad wrote:
> 
> 
> On 06-06-2024 11:24, Riana Tauro wrote:
>> The rc6 registers used in disable_c6 function belong
>> to the GT forcewake domain. Hence change the forcewake
>> assertion to check GT forcewake domain.
> 
> I think this should go with fixes tag.
> with that
> Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray at intel.com>
Thanks for the review. Will add the fixes tag and resend
> 
>>
>> Signed-off-by: Riana Tauro <riana.tauro at intel.com>
>> Reviewed-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
>> ---
>>   drivers/gpu/drm/xe/xe_gt_idle.c | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_gt_idle.c 
>> b/drivers/gpu/drm/xe/xe_gt_idle.c
>> index 0109d1d2e9c4..a6ab8bb4571d 100644
>> --- a/drivers/gpu/drm/xe/xe_gt_idle.c
>> +++ b/drivers/gpu/drm/xe/xe_gt_idle.c
>> @@ -250,7 +250,7 @@ void xe_gt_idle_enable_c6(struct xe_gt *gt)
>>   void xe_gt_idle_disable_c6(struct xe_gt *gt)
>>   {
>>       xe_device_assert_mem_access(gt_to_xe(gt));
>> -    xe_force_wake_assert_held(gt_to_fw(gt), XE_FORCEWAKE_ALL);
>> +    xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);
>>       xe_mmio_write32(gt, RC_CONTROL, 0);
>>       xe_mmio_write32(gt, RC_STATE, 0);