[PATCH v5 02/10] drm/xe: Add MI_COPY_MEM_MEM GPU instruction definitions

[Cavitt, Jonathan]

-----Original Message-----
> From: Intel-xe <intel-xe-bounces at lists.freedesktop.org> On Behalf Of Matthew Brost
> Sent: Monday, June 10, 2024 7:18 AM
> To: intel-xe at lists.freedesktop.org
> Subject: [PATCH v5 02/10] drm/xe: Add MI_COPY_MEM_MEM GPU instruction definitions
> 
> MI_COPY_MEM_MEM GPU instructions are used to copy ctx timestamp from a
> LRC registers to another location at the beginning of every jobs
> execution. Add MI_COPY_MEM_MEM GPU instruction definitions.
> 
> v2:
>  - Include MI_COPY_MEM_MEM based on instruction order (Michal)
>  - Fix tabs/spaces issue (Michal)
>  - Use macro for DW definition (Michal)
> 
> Signed-off-by: Matthew Brost <matthew.brost at intel.com>

It might be worth considering having these definitions included with the patches
that use them, but I can understand why the declarations were done separately
and agree this is probably better.
Reviewed-by: Jonathan Cavitt <jonathan.cavitt at intel.com>
> ---
>  drivers/gpu/drm/xe/instructions/xe_mi_commands.h | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/instructions/xe_mi_commands.h b/drivers/gpu/drm/xe/instructions/xe_mi_commands.h
> index c74ceb550dce..b7bf99dd4848 100644
> --- a/drivers/gpu/drm/xe/instructions/xe_mi_commands.h
> +++ b/drivers/gpu/drm/xe/instructions/xe_mi_commands.h
> @@ -59,6 +59,10 @@
>  #define MI_LOAD_REGISTER_MEM		(__MI_INSTR(0x29) | XE_INSTR_NUM_DW(4))
>  #define   MI_LRM_USE_GGTT		REG_BIT(22)
>  
> +#define MI_COPY_MEM_MEM			(__MI_INSTR(0x2e) | XE_INSTR_NUM_DW(5))
> +#define   MI_COPY_MEM_MEM_SRC_GGTT	REG_BIT(22)
> +#define   MI_COPY_MEM_MEM_DST_GGTT	REG_BIT(21)
> +
>  #define MI_BATCH_BUFFER_START		__MI_INSTR(0x31)
>  
>  #endif
> -- 
> 2.34.1
> 
>