[PATCH v11 0/5] drm/xe/guc: Add GuC based register capture for error capture
Zhanjun Dong
zhanjun.dong at intel.com
Mon Jun 24 21:53:59 UTC 2024
Port GuC based register capture for error capture from i915 to Xe.
There are 3 parts inside:
. Prepare for capture registers
There is a bo create at guc ads init time, that is very early
and engi ne map is not ready, make it hard to calculate the
capture buffer size, new function created for worst case size
caluation. Other than that, this part basically follows the i915
design.
. Process capture notification message
Basically follows i915 design
. Sysfs command process.
Xe switched to devcoredump, adopted command line process with
captured node list.
Signed-off-by: Zhanjun Dong <zhanjun.dong at intel.com>
Cc: Alan Previn <alan.previn.teres.alexis at intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko at intel.com>
Changes from prior revs:
v11:- Fixed a bug of missing captured check on register snapshot pre-capture
Fixed kernel-doc warnings
v10:- Resync with updated job timed out follow
Add pre-capture by read from hw engine if GuC capture data is not
ready, the pre-captured data will be refereshed if GuC capture is
ready at later time.
Add xe_guc_capture_is_ready_for to check if GuC capture is ready
for a job.
Re-orgnize some header files to xe abi folder
Reduce some meesage level from warn/info to debug
Remove duplicated enum of GuC log type.
v9:- Merged snapshot register list into capture register lists
Optimized devcoredump timing to take snapshot after guc reset
Add global and engine class registers into capture list
Fixed bug of incorrect matching guc class id with guc capture class id
v8:- Reorgnize the order of patches
Change the capture size check from worst min size to worst size
Replace the kernel alloc with drm managed alloc
Replace the memcpy with xe_map_memcpy_from
Free GuC capture outlist as part of xe_devcoredump_free
v7:- Kconfig CONFIG_DRM_XE_CAPTURE_ERROR removed
v6:- Change hardcoded register snapshot fill to follow mapping tables
When capture is empty, take snapshot from engine
v5:- Split dss helper code out as an standalone patch
Remove old platform registers definition.
Split register map table to 32 and 64bit each
v4:- Move register map table to xe_hw_engine.c
v3:- Remove condition compilation in code
v2:- Split into multiple chunks
Zhanjun Dong (5):
drm/xe/guc: Prepare GuC register list and update ADS size for error
capture
drm/xe/guc: Add XE_LP steered register lists
drm/xe/guc: Add capture size check in GuC log buffer
drm/xe/guc: Extract GuC error capture lists
drm/xe/guc: Plumb GuC-capture into dev coredump
drivers/gpu/drm/xe/Makefile | 1 +
drivers/gpu/drm/xe/abi/guc_actions_abi.h | 8 +
drivers/gpu/drm/xe/abi/guc_capture_abi.h | 78 +
drivers/gpu/drm/xe/abi/guc_log_abi.h | 59 +
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 +
drivers/gpu/drm/xe/xe_devcoredump.c | 15 +-
drivers/gpu/drm/xe/xe_devcoredump_types.h | 2 +
drivers/gpu/drm/xe/xe_guc.c | 5 +
drivers/gpu/drm/xe/xe_guc.h | 28 +
drivers/gpu/drm/xe/xe_guc_ads.c | 157 ++-
drivers/gpu/drm/xe/xe_guc_ads_types.h | 2 +
drivers/gpu/drm/xe/xe_guc_capture.c | 1564 +++++++++++++++++++++
drivers/gpu/drm/xe/xe_guc_capture.h | 56 +
drivers/gpu/drm/xe/xe_guc_capture_types.h | 133 ++
drivers/gpu/drm/xe/xe_guc_ct.c | 2 +
drivers/gpu/drm/xe/xe_guc_fwif.h | 32 +
drivers/gpu/drm/xe/xe_guc_log.c | 205 +++
drivers/gpu/drm/xe/xe_guc_log.h | 17 +-
drivers/gpu/drm/xe/xe_guc_log_types.h | 18 +
drivers/gpu/drm/xe/xe_guc_submit.c | 83 +-
drivers/gpu/drm/xe/xe_guc_submit.h | 2 +
drivers/gpu/drm/xe/xe_guc_types.h | 2 +
drivers/gpu/drm/xe/xe_hw_engine.c | 242 +++-
drivers/gpu/drm/xe/xe_hw_engine.h | 2 +
drivers/gpu/drm/xe/xe_hw_engine_types.h | 176 ++-
drivers/gpu/drm/xe/xe_lrc.h | 1 +
26 files changed, 2715 insertions(+), 177 deletions(-)
create mode 100644 drivers/gpu/drm/xe/abi/guc_capture_abi.h
create mode 100644 drivers/gpu/drm/xe/abi/guc_log_abi.h
create mode 100644 drivers/gpu/drm/xe/xe_guc_capture.c
create mode 100644 drivers/gpu/drm/xe/xe_guc_capture.h
create mode 100644 drivers/gpu/drm/xe/xe_guc_capture_types.h
--
2.34.1
More information about the Intel-xe
mailing list