✓ CI.checkpatch: success for drm/xe/guc: Configure TLB timeout based on CT buffer size

[Patchwork]

== Series Details ==

Series: drm/xe/guc: Configure TLB timeout based on CT buffer size
URL   : https://patchwork.freedesktop.org/series/135341/
State : success

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
51ce9f6cd981d42d7467409d7dbc559a450abc1e
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 555c13e65922f280cca44f0135c874681fa4b589
Author: Nirmoy Das <nirmoy.das at intel.com>
Date:   Tue Jun 25 10:49:47 2024 +0200

    drm/xe/guc: Configure TLB timeout based on CT buffer size
    
    GuC TLB invalidation depends on GuC to process the request from the CT
    queue and then the real time to invalidate TLB. Add a function to return
    overestimated possible time a TLB inval H2G might take which can be used
    as timeout value for TLB invalidation wait time.
    
    Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/1622
    Cc: Matthew Brost <matthew.brost at intel.com>
    Suggested-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>
    Signed-off-by: Nirmoy Das <nirmoy.das at intel.com>
+ /mt/dim checkpatch 5e45785f315938951d86af616d35a5ba08bfeabc drm-intel
555c13e65922 drm/xe/guc: Configure TLB timeout based on CT buffer size