[PATCH 2/3] drm/xe: Introduce no_preempt exec queue op
Ashutosh Dixit
ashutosh.dixit at intel.com
Tue Jun 25 20:05:57 UTC 2024
Introduce no_preempt exec queue op to allow an exec queue to run
uninterrupted (without preemption or timeslicing). The functionality is
used in OA in the next patch.
Cc: Matthew Brost <matthew.brost at intel.com>
Signed-off-by: Ashutosh Dixit <ashutosh.dixit at intel.com>
---
drivers/gpu/drm/xe/xe_exec_queue_types.h | 2 ++
drivers/gpu/drm/xe/xe_execlist.c | 7 +++++
drivers/gpu/drm/xe/xe_guc_submit.c | 36 ++++++++++++++++++++++++
3 files changed, 45 insertions(+)
diff --git a/drivers/gpu/drm/xe/xe_exec_queue_types.h b/drivers/gpu/drm/xe/xe_exec_queue_types.h
index 201588ec33c3..52e281158b15 100644
--- a/drivers/gpu/drm/xe/xe_exec_queue_types.h
+++ b/drivers/gpu/drm/xe/xe_exec_queue_types.h
@@ -164,6 +164,8 @@ struct xe_exec_queue_ops {
int (*set_timeslice)(struct xe_exec_queue *q, u32 timeslice_us);
/** @set_preempt_timeout: Set preemption timeout for exec queue */
int (*set_preempt_timeout)(struct xe_exec_queue *q, u32 preempt_timeout_us);
+ /** @no_preempt: Disable preemption and timeslicing for exec queue */
+ int (*no_preempt)(struct xe_exec_queue *q, bool enable);
/**
* @suspend: Suspend exec queue from executing, allowed to be called
* multiple times in a row before resume with the caveat that
diff --git a/drivers/gpu/drm/xe/xe_execlist.c b/drivers/gpu/drm/xe/xe_execlist.c
index db906117db6d..15392c1d7005 100644
--- a/drivers/gpu/drm/xe/xe_execlist.c
+++ b/drivers/gpu/drm/xe/xe_execlist.c
@@ -416,6 +416,12 @@ static int execlist_exec_queue_set_preempt_timeout(struct xe_exec_queue *q,
return 0;
}
+static int execlist_exec_queue_no_preempt(struct xe_exec_queue *q, bool enable)
+{
+ /* NIY */
+ return 0;
+}
+
static int execlist_exec_queue_suspend(struct xe_exec_queue *q)
{
/* NIY */
@@ -446,6 +452,7 @@ static const struct xe_exec_queue_ops execlist_exec_queue_ops = {
.set_priority = execlist_exec_queue_set_priority,
.set_timeslice = execlist_exec_queue_set_timeslice,
.set_preempt_timeout = execlist_exec_queue_set_preempt_timeout,
+ .no_preempt = execlist_exec_queue_no_preempt,
.suspend = execlist_exec_queue_suspend,
.suspend_wait = execlist_exec_queue_suspend_wait,
.resume = execlist_exec_queue_resume,
diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c
index 373447758a60..db424133bc14 100644
--- a/drivers/gpu/drm/xe/xe_guc_submit.c
+++ b/drivers/gpu/drm/xe/xe_guc_submit.c
@@ -1548,6 +1548,41 @@ static int guc_exec_queue_set_preempt_timeout(struct xe_exec_queue *q,
return 0;
}
+static int guc_exec_queue_no_preempt(struct xe_exec_queue *q, bool enable)
+{
+ struct xe_sched_msg *msg;
+
+ if (exec_queue_killed_or_banned_or_wedged(q))
+ return 0;
+
+ if (enable) {
+ if (!q->sched_props.preempt_timeout_us && !q->sched_props.timeslice_us)
+ return 0;
+ } else {
+ if (q->sched_props.preempt_timeout_us ==
+ q->hwe->eclass->sched_props.preempt_timeout_us &&
+ q->sched_props.timeslice_us == q->hwe->eclass->sched_props.timeslice_us)
+ return 0;
+ }
+
+ msg = kmalloc(sizeof(*msg), GFP_KERNEL);
+ if (!msg)
+ return -ENOMEM;
+
+ if (enable) {
+ /* Setting values to 0 will disable preemption and timeslicing */
+ q->sched_props.preempt_timeout_us = 0;
+ q->sched_props.timeslice_us = 0;
+ } else {
+ q->sched_props.preempt_timeout_us = q->hwe->eclass->sched_props.preempt_timeout_us;
+ q->sched_props.timeslice_us = q->hwe->eclass->sched_props.timeslice_us;
+ }
+
+ guc_exec_queue_add_msg(q, msg, SET_SCHED_PROPS);
+
+ return 0;
+}
+
static int guc_exec_queue_suspend(struct xe_exec_queue *q)
{
struct xe_sched_msg *msg = q->guc->static_msgs + STATIC_MSG_SUSPEND;
@@ -1598,6 +1633,7 @@ static const struct xe_exec_queue_ops guc_exec_queue_ops = {
.set_priority = guc_exec_queue_set_priority,
.set_timeslice = guc_exec_queue_set_timeslice,
.set_preempt_timeout = guc_exec_queue_set_preempt_timeout,
+ .no_preempt = guc_exec_queue_no_preempt,
.suspend = guc_exec_queue_suspend,
.suspend_wait = guc_exec_queue_suspend_wait,
.resume = guc_exec_queue_resume,
--
2.41.0
More information about the Intel-xe
mailing list