✗ CI.checkpatch: warning for drm/xe/gsc: Handle GSCCS ER interrupt (rev3)

[Patchwork]

== Series Details ==

Series: drm/xe/gsc: Handle GSCCS ER interrupt (rev3)
URL   : https://patchwork.freedesktop.org/series/129182/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
a9eb1ac8298ef9f9146567c29fa762d8e9efa1ef
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 6688d6e5766b304222080c4303762e54a7676c16
Author: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>
Date:   Mon Mar 4 06:56:34 2024 -0800

    drm/xe/gsc: Handle GSCCS ER interrupt
    
    Starting on Xe2, the GSCCS engine reset is a 2-step process. When the
    driver or the GuC hits the GDRST register, the CS is immediately reset
    and a success is reported, but the GSC shim continues its reset in the
    background. While the shim reset is ongoing, the CS is able to accept
    new context submission, but any commands that require the shim will
    be stalled until the reset is completed. This means that we can keep
    submitting to the GSCCS as long as we make sure that the preemption
    timeout is big enough to cover any delay introduced by the reset; since
    the GSC preempt timeout is not tunable at runtime, we only need to check
    that the value set in kconfig is big enough (and increase it if it
    isn't).
    When the shim reset completes, a specific CS interrupt is triggered,
    in response to which we need to check the GSCI_TIMER_STATUS register
    to see if the reset was successful or not.
    Note that the GSCI_TIMER_STATUS register is not power save/restored,
    so it gets reset on MC6 entry. However, a reset failure stops MC6,
    so in that scenario we're always guaranteed to find the correct value.
    
    Since we can't check the register within interrupt context, the
    existing GSC worker has been updated to handle it.
    The expected action to take on ER failure is to trigger a driver FLR,
    but we still don't support that, so for now we just print an error. A
    comment has been added to the code to keep track of the FLR requirement.
    
    v2: Add a check for the initial timeout value (Alan)
    
    Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>
    Cc: Alan Previn <alan.previn.teres.alexis at intel.com>
    Reviewed-by: Alan Previn <alan.previn.teres.alexis at intel.com>
+ /mt/dim checkpatch f5246a1cf97dd1b9bf955148b0ca2cbf0b18d31e drm-intel
6688d6e5766b drm/xe/gsc: Handle GSCCS ER interrupt
-:220: WARNING:TYPO_SPELLING: 'preemptable' may be misspelled - perhaps 'preemptible'?
#220: FILE: drivers/gpu/drm/xe/xe_hw_engine.c:475:
+		 * without being preemptable, which means worst case it can
 		                 ^^^^^^^^^^^

-:233: WARNING:LINE_SPACING: Missing a blank line after declarations
#233: FILE: drivers/gpu/drm/xe/xe_hw_engine.c:488:
+			const u32 min_preempt_timeout = 600 * 1000;
+			if (hwe->eclass->sched_props.preempt_timeout_us < min_preempt_timeout) {

total: 0 errors, 2 warnings, 0 checks, 194 lines checked