[PATCH] drm/xe/display: mark DPT with XE_BO_PAGETABLE

[Juha-Pekka Heikkila]

Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>

On 14.3.2024 18.49, Matthew Auld wrote:
> Otherwise in the case where we use normal system memory, the CPU access
> will always be cached, like when filling the DPT PTEs, which is likely
> not what we want since HW access could be incoherent on platforms like
> LNL. Marking as XE_BO_PAGETABLE will force wc/uc underneath on such
> platforms.
> 
> Signed-off-by: Matthew Auld <matthew.auld at intel.com>
> Cc: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>
> ---
>   drivers/gpu/drm/xe/display/xe_fb_pin.c | 9 ++++++---
>   1 file changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c
> index 722c84a56607..b220f136be70 100644
> --- a/drivers/gpu/drm/xe/display/xe_fb_pin.c
> +++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c
> @@ -100,17 +100,20 @@ static int __xe_pin_fb_vma_dpt(struct intel_framebuffer *fb,
>   		dpt = xe_bo_create_pin_map(xe, tile0, NULL, dpt_size,
>   					   ttm_bo_type_kernel,
>   					   XE_BO_CREATE_VRAM0_BIT |
> -					   XE_BO_CREATE_GGTT_BIT);
> +					   XE_BO_CREATE_GGTT_BIT |
> +					   XE_BO_PAGETABLE);
>   	else
>   		dpt = xe_bo_create_pin_map(xe, tile0, NULL, dpt_size,
>   					   ttm_bo_type_kernel,
>   					   XE_BO_CREATE_STOLEN_BIT |
> -					   XE_BO_CREATE_GGTT_BIT);
> +					   XE_BO_CREATE_GGTT_BIT |
> +					   XE_BO_PAGETABLE);
>   	if (IS_ERR(dpt))
>   		dpt = xe_bo_create_pin_map(xe, tile0, NULL, dpt_size,
>   					   ttm_bo_type_kernel,
>   					   XE_BO_CREATE_SYSTEM_BIT |
> -					   XE_BO_CREATE_GGTT_BIT);
> +					   XE_BO_CREATE_GGTT_BIT |
> +					   XE_BO_PAGETABLE);
>   	if (IS_ERR(dpt))
>   		return PTR_ERR(dpt);
>