✓ CI.checkpatch: success for drm/xe/display: mark DPT with XE_BO_PAGETABLE

[Patchwork]

== Series Details ==

Series: drm/xe/display: mark DPT with XE_BO_PAGETABLE
URL   : https://patchwork.freedesktop.org/series/131148/
State : success

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
a9eb1ac8298ef9f9146567c29fa762d8e9efa1ef
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit d51b19e43033646cd476557bef0f13ee47118333
Author: Matthew Auld <matthew.auld at intel.com>
Date:   Thu Mar 14 16:49:06 2024 +0000

    drm/xe/display: mark DPT with XE_BO_PAGETABLE
    
    Otherwise in the case where we use normal system memory, the CPU access
    will always be cached, like when filling the DPT PTEs, which is likely
    not what we want since HW access could be incoherent on platforms like
    LNL. Marking as XE_BO_PAGETABLE will force wc/uc underneath on such
    platforms.
    
    Signed-off-by: Matthew Auld <matthew.auld at intel.com>
    Cc: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>
    Reviewed-by: Lucas De Marchi <lucas.demarchi at intel.com>
    Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>
+ /mt/dim checkpatch f5246a1cf97dd1b9bf955148b0ca2cbf0b18d31e drm-intel
d51b19e43033 drm/xe/display: mark DPT with XE_BO_PAGETABLE