[PATCH v2 5/6] drm/xe: Mark VF accessible interrupt registers

[Matt Roper]

On Thu, Mar 14, 2024 at 06:31:29PM +0100, Michal Wajdeczko wrote:
> Interrupt registers 1900xx are VF accessible but only until version
> 12.50 as on newer platforms VFs are using memory-based interrupts.
> 
> To avoid complexity, we mark those registers with XE_REG_OPTION_VF
> unconditionally, as IRQ handling on newer VFs is different anyway.
> 
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko at intel.com>
> Cc: Matt Roper <matthew.d.roper at intel.com>

Reviewed-by: Matt Roper <matthew.d.roper at intel.com>

> ---
> v2: explain when those regs are really VFs accessible (Matt)
> ---
>  drivers/gpu/drm/xe/regs/xe_gt_regs.h | 40 ++++++++++++++++------------
>  1 file changed, 23 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index 15ac2d284d48..9513a11c5236 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -439,7 +439,13 @@
>  #define GT_PERF_STATUS				XE_REG(0x1381b4)
>  #define   VOLTAGE_MASK				REG_GENMASK(10, 0)
>  
> -#define GT_INTR_DW(x)				XE_REG(0x190018 + ((x) * 4))
> +/*
> + * Note: Interrupt registers 1900xx are VF accessible only until version 12.50.
> + *       On newer platforms, VFs are using memory-based interrupts instead.
> + *       However, for simplicity we keep this XE_REG_OPTION_VF tag intact.
> + */
> +
> +#define GT_INTR_DW(x)				XE_REG(0x190018 + ((x) * 4), XE_REG_OPTION_VF)
>  #define   INTR_GSC				REG_BIT(31)
>  #define   INTR_GUC				REG_BIT(25)
>  #define   INTR_MGUC				REG_BIT(24)
> @@ -450,16 +456,16 @@
>  #define   INTR_VECS(x)				REG_BIT(31 - (x))
>  #define   INTR_VCS(x)				REG_BIT(x)
>  
> -#define RENDER_COPY_INTR_ENABLE			XE_REG(0x190030)
> -#define VCS_VECS_INTR_ENABLE			XE_REG(0x190034)
> -#define GUC_SG_INTR_ENABLE			XE_REG(0x190038)
> +#define RENDER_COPY_INTR_ENABLE			XE_REG(0x190030, XE_REG_OPTION_VF)
> +#define VCS_VECS_INTR_ENABLE			XE_REG(0x190034, XE_REG_OPTION_VF)
> +#define GUC_SG_INTR_ENABLE			XE_REG(0x190038, XE_REG_OPTION_VF)
>  #define   ENGINE1_MASK				REG_GENMASK(31, 16)
>  #define   ENGINE0_MASK				REG_GENMASK(15, 0)
> -#define GPM_WGBOXPERF_INTR_ENABLE		XE_REG(0x19003c)
> -#define GUNIT_GSC_INTR_ENABLE			XE_REG(0x190044)
> -#define CCS_RSVD_INTR_ENABLE			XE_REG(0x190048)
> +#define GPM_WGBOXPERF_INTR_ENABLE		XE_REG(0x19003c, XE_REG_OPTION_VF)
> +#define GUNIT_GSC_INTR_ENABLE			XE_REG(0x190044, XE_REG_OPTION_VF)
> +#define CCS_RSVD_INTR_ENABLE			XE_REG(0x190048, XE_REG_OPTION_VF)
>  
> -#define INTR_IDENTITY_REG(x)			XE_REG(0x190060 + ((x) * 4))
> +#define INTR_IDENTITY_REG(x)			XE_REG(0x190060 + ((x) * 4), XE_REG_OPTION_VF)
>  #define   INTR_DATA_VALID			REG_BIT(31)
>  #define   INTR_ENGINE_INSTANCE(x)		REG_FIELD_GET(GENMASK(25, 20), x)
>  #define   INTR_ENGINE_CLASS(x)			REG_FIELD_GET(GENMASK(18, 16), x)
> @@ -468,16 +474,16 @@
>  #define   OTHER_GSC_HECI2_INSTANCE		3
>  #define   OTHER_GSC_INSTANCE			6
>  
> -#define IIR_REG_SELECTOR(x)			XE_REG(0x190070 + ((x) * 4))
> -#define RCS0_RSVD_INTR_MASK			XE_REG(0x190090)
> -#define BCS_RSVD_INTR_MASK			XE_REG(0x1900a0)
> -#define VCS0_VCS1_INTR_MASK			XE_REG(0x1900a8)
> -#define VCS2_VCS3_INTR_MASK			XE_REG(0x1900ac)
> -#define VECS0_VECS1_INTR_MASK			XE_REG(0x1900d0)
> +#define IIR_REG_SELECTOR(x)			XE_REG(0x190070 + ((x) * 4), XE_REG_OPTION_VF)
> +#define RCS0_RSVD_INTR_MASK			XE_REG(0x190090, XE_REG_OPTION_VF)
> +#define BCS_RSVD_INTR_MASK			XE_REG(0x1900a0, XE_REG_OPTION_VF)
> +#define VCS0_VCS1_INTR_MASK			XE_REG(0x1900a8, XE_REG_OPTION_VF)
> +#define VCS2_VCS3_INTR_MASK			XE_REG(0x1900ac, XE_REG_OPTION_VF)
> +#define VECS0_VECS1_INTR_MASK			XE_REG(0x1900d0, XE_REG_OPTION_VF)
>  #define HECI2_RSVD_INTR_MASK			XE_REG(0x1900e4)
> -#define GUC_SG_INTR_MASK			XE_REG(0x1900e8)
> -#define GPM_WGBOXPERF_INTR_MASK			XE_REG(0x1900ec)
> -#define GUNIT_GSC_INTR_MASK			XE_REG(0x1900f4)
> +#define GUC_SG_INTR_MASK			XE_REG(0x1900e8, XE_REG_OPTION_VF)
> +#define GPM_WGBOXPERF_INTR_MASK			XE_REG(0x1900ec, XE_REG_OPTION_VF)
> +#define GUNIT_GSC_INTR_MASK			XE_REG(0x1900f4, XE_REG_OPTION_VF)
>  #define CCS0_CCS1_INTR_MASK			XE_REG(0x190100)
>  #define CCS2_CCS3_INTR_MASK			XE_REG(0x190104)
>  #define XEHPC_BCS1_BCS2_INTR_MASK		XE_REG(0x190110)
> -- 
> 2.43.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation