[PATCH] drm/xe: Use FIELD_PREP for lrc descriptor

Niranjana Vishwanathapura niranjana.vishwanathapura at intel.com
Thu Mar 21 16:52:21 UTC 2024


On Thu, Mar 21, 2024 at 09:29:19AM -0500, Lucas De Marchi wrote:
>On Wed, Mar 20, 2024 at 10:47:15PM -0700, Niranjana Vishwanathapura wrote:
>>Use FIELD_PREP for setting lrc descriptor fields instead
>>of shifting values to fields.
>>
>>Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura at intel.com>
>>---
>>drivers/gpu/drm/xe/xe_lrc.c | 20 ++++++++++----------
>>1 file changed, 10 insertions(+), 10 deletions(-)
>>
>>diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
>>index 95e0f7b1ec3f..f07ee9d8b856 100644
>>--- a/drivers/gpu/drm/xe/xe_lrc.c
>>+++ b/drivers/gpu/drm/xe/xe_lrc.c
>>@@ -26,13 +26,13 @@
>>#include "xe_sriov.h"
>>#include "xe_vm.h"
>>
>>-#define LRC_VALID				(1 << 0)
>>-#define LRC_PRIVILEGE				(1 << 8)
>>-#define LRC_ADDRESSING_MODE_SHIFT		3
>>+#define LRC_VALID				BIT(0)
>>+#define LRC_PRIVILEGE				BIT(8)
>>+#define LRC_ADDRESSING_MODE			GENMASK(4, 3)
>>#define LRC_LEGACY_64B_CONTEXT			3
>>
>>-#define ENGINE_CLASS_SHIFT			61
>>-#define ENGINE_INSTANCE_SHIFT			48
>>+#define LRC_ENGINE_CLASS			GENMASK(63, 61)
>
>you will either need to use GENMASK_ULL() or wait us having
>GENMASK_U64() available. This will break the build in arch=i386
>

Thanks, I have reposted the patch with the fix.

Niranjana

>Lucas De Marchi
>
>>+#define LRC_ENGINE_INSTANCE			GENMASK(53, 48)
>>
>>struct xe_lrc_snapshot {
>>	struct xe_bo *lrc_bo;
>>@@ -797,19 +797,19 @@ int xe_lrc_init(struct xe_lrc *lrc, struct xe_hw_engine *hwe,
>>	if (xe->info.has_asid && vm)
>>		xe_lrc_write_ctx_reg(lrc, PVC_CTX_ASID, vm->usm.asid);
>>
>>-	lrc->desc = LRC_VALID;
>>-	lrc->desc |= LRC_LEGACY_64B_CONTEXT << LRC_ADDRESSING_MODE_SHIFT;
>>+	lrc->desc = FIELD_PREP(LRC_VALID, 1);
>>+	lrc->desc |= FIELD_PREP(LRC_ADDRESSING_MODE, LRC_LEGACY_64B_CONTEXT);
>>	/* TODO: Priority */
>>
>>	/* While this appears to have something about privileged batches or
>>	 * some such, it really just means PPGTT mode.
>>	 */
>>	if (vm)
>>-		lrc->desc |= LRC_PRIVILEGE;
>>+		lrc->desc |= FIELD_PREP(LRC_PRIVILEGE, 1);
>>
>>	if (GRAPHICS_VERx100(xe) < 1250) {
>>-		lrc->desc |= (u64)hwe->instance << ENGINE_INSTANCE_SHIFT;
>>-		lrc->desc |= (u64)hwe->class << ENGINE_CLASS_SHIFT;
>>+		lrc->desc |= FIELD_PREP(LRC_ENGINE_INSTANCE, hwe->instance);
>>+		lrc->desc |= FIELD_PREP(LRC_ENGINE_CLASS, hwe->class);
>>	}
>>
>>	arb_enable = MI_ARB_ON_OFF | MI_ARB_ENABLE;
>>-- 
>>2.43.0
>>


More information about the Intel-xe mailing list