[PATCH] drm/xe/gsc: Implement WA 14018094691

[Matt Roper]

On Wed, Mar 20, 2024 at 02:18:19PM -0700, Daniele Ceraolo Spurio wrote:
> The WA states that we need to keep the primary GT powered up during GSC
> load to allow the GSC FW to access its registers. We also need to make
> sure that one of the registers is locked before starting the load.
> 
> Bspec: 55928
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>
> ---
>  drivers/gpu/drm/xe/regs/xe_gt_regs.h |  3 +++
>  drivers/gpu/drm/xe/xe_gsc.c          | 22 ++++++++++++++++++++++
>  drivers/gpu/drm/xe/xe_wa_oob.rules   |  1 +
>  3 files changed, 26 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index 95969935f58b..713e4d590fc0 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -373,6 +373,9 @@
>  #define   LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK	REG_GENMASK(13, 11)
>  #define   DIS_ATOMIC_CHAINING_TYPED_WRITES	REG_BIT(3)
>  
> +#define EU_SYSTOLIC_LIC_THROTTLE_CTL_WITH_LOCK	XE_REG_MCR(0xe534)
> +#define   EU_SYSTOLIC_LIC_THROTTLE_CTL_LOCK_BIT	REG_BIT(31)

It's not obvious from the context here, but I think this should be
slightly higher in the file, before the XEHP_HDC_CHICKEN0 definition.

Otherwise,

Reviewed-by: Matt Roper <matthew.d.roper at intel.com>

> +
>  #define LSC_CHICKEN_BIT_0			XE_REG_MCR(0xe7c8)
>  #define   DISABLE_D8_D16_COASLESCE		REG_BIT(30)
>  #define   TGM_WRITE_EOM_FORCE			REG_BIT(17)
> diff --git a/drivers/gpu/drm/xe/xe_gsc.c b/drivers/gpu/drm/xe/xe_gsc.c
> index 09f6e7899921..c9a139d45095 100644
> --- a/drivers/gpu/drm/xe/xe_gsc.c
> +++ b/drivers/gpu/drm/xe/xe_gsc.c
> @@ -17,6 +17,7 @@
>  #include "xe_gsc_proxy.h"
>  #include "xe_gsc_submit.h"
>  #include "xe_gt.h"
> +#include "xe_gt_mcr.h"
>  #include "xe_gt_printk.h"
>  #include "xe_huc.h"
>  #include "xe_map.h"
> @@ -252,9 +253,30 @@ static int gsc_upload(struct xe_gsc *gsc)
>  static int gsc_upload_and_init(struct xe_gsc *gsc)
>  {
>  	struct xe_gt *gt = gsc_to_gt(gsc);
> +	struct xe_tile *tile = gt_to_tile(gt);
>  	int ret;
>  
> +	if (XE_WA(gt, 14018094691)) {
> +		ret = xe_force_wake_get(gt_to_fw(tile->primary_gt), XE_FORCEWAKE_ALL);
> +
> +		/*
> +		 * If the forcewake fails we want to keep going, because the worst
> +		 * case outcome in failing to apply the WA is that PXP won't work,
> +		 * which is not fatal. We still throw a warning so the issue is
> +		 * seen if it happens.
> +		 */
> +		xe_gt_WARN_ON(tile->primary_gt, ret);
> +
> +		xe_gt_mcr_multicast_write(tile->primary_gt,
> +					  EU_SYSTOLIC_LIC_THROTTLE_CTL_WITH_LOCK,
> +					  EU_SYSTOLIC_LIC_THROTTLE_CTL_LOCK_BIT);
> +	}
> +
>  	ret = gsc_upload(gsc);
> +
> +	if (XE_WA(gt, 14018094691))
> +		xe_force_wake_put(gt_to_fw(tile->primary_gt), XE_FORCEWAKE_ALL);
> +
>  	if (ret)
>  		return ret;
>  
> diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
> index 48cdba1cbf95..68600cdead84 100644
> --- a/drivers/gpu/drm/xe/xe_wa_oob.rules
> +++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
> @@ -19,3 +19,4 @@
>  		GRAPHICS_VERSION_RANGE(1270, 1274)
>  		MEDIA_VERSION(1300)
>  		PLATFORM(DG2)
> +14018094691	GRAPHICS_VERSION(2004)
> -- 
> 2.43.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation