[PATCH v4 2/2] drm/xe/mocs: Add debugfs node to dump mocs
Lucas De Marchi
lucas.demarchi at intel.com
Wed May 1 21:04:51 UTC 2024
On Tue, Apr 30, 2024 at 10:34:27PM GMT, Janga Rahul Kumar wrote:
>This is useful to check mocs configuration. Tests/Tools can use
>this debugfs entry to get mocs info.
>
>v2: Address review comments. Change debugfs output style similar
>to pat debugfs. (Lucas De Marchi)
>
>v3: rebase.
>
>v4: Address review comments. Use function pointer inside ops
>struct. Update Test-with links. Remove usage of flags wherever
>not required. (Lucas De Marchi)
>
>Test-with: https://patchwork.freedesktop.org/patch/msgid/20240424200856.1194881-2-janga.rahul.kumar@intel.com
> https://patchwork.freedesktop.org/patch/msgid/20240424200856.1194881-3-janga.rahul.kumar@intel.com/
only in the cover ^
>
>Cc: Matt Roper <matthew.d.roper at intel.com>
>Cc: Lucas De Marchi <lucas.demarchi at intel.com>
>Signed-off-by: Janga Rahul Kumar <janga.rahul.kumar at intel.com>
>---
> drivers/gpu/drm/xe/xe_gt_debugfs.c | 11 ++
> drivers/gpu/drm/xe/xe_mocs.c | 258 +++++++++++++++++++++++++++++
> drivers/gpu/drm/xe/xe_mocs.h | 8 +
> 3 files changed, 277 insertions(+)
>
>diff --git a/drivers/gpu/drm/xe/xe_gt_debugfs.c b/drivers/gpu/drm/xe/xe_gt_debugfs.c
>index 599aed47f2ba..84068acbef4b 100644
>--- a/drivers/gpu/drm/xe/xe_gt_debugfs.c
>+++ b/drivers/gpu/drm/xe/xe_gt_debugfs.c
>@@ -18,6 +18,7 @@
> #include "xe_hw_engine.h"
> #include "xe_lrc.h"
> #include "xe_macros.h"
>+#include "xe_mocs.h"
> #include "xe_pat.h"
> #include "xe_pm.h"
> #include "xe_reg_sr.h"
>@@ -200,6 +201,15 @@ static int pat(struct xe_gt *gt, struct drm_printer *p)
> return 0;
> }
>
>+static int mocs(struct xe_gt *gt, struct drm_printer *p)
>+{
>+ xe_pm_runtime_get(gt_to_xe(gt));
>+ xe_mocs_dump(gt, p);
>+ xe_pm_runtime_put(gt_to_xe(gt));
>+
>+ return 0;
>+}
>+
> static int rcs_default_lrc(struct xe_gt *gt, struct drm_printer *p)
> {
> xe_pm_runtime_get(gt_to_xe(gt));
>@@ -255,6 +265,7 @@ static const struct drm_info_list debugfs_list[] = {
> {"register-save-restore", .show = xe_gt_debugfs_simple_show, .data = register_save_restore},
> {"workarounds", .show = xe_gt_debugfs_simple_show, .data = workarounds},
> {"pat", .show = xe_gt_debugfs_simple_show, .data = pat},
>+ {"mocs", .show = xe_gt_debugfs_simple_show, .data = mocs},
> {"default_lrc_rcs", .show = xe_gt_debugfs_simple_show, .data = rcs_default_lrc},
> {"default_lrc_ccs", .show = xe_gt_debugfs_simple_show, .data = ccs_default_lrc},
> {"default_lrc_bcs", .show = xe_gt_debugfs_simple_show, .data = bcs_default_lrc},
>diff --git a/drivers/gpu/drm/xe/xe_mocs.c b/drivers/gpu/drm/xe/xe_mocs.c
>index aef09eb423e9..a7caa9df0470 100644
>--- a/drivers/gpu/drm/xe/xe_mocs.c
>+++ b/drivers/gpu/drm/xe/xe_mocs.c
>@@ -13,6 +13,7 @@
> #include "xe_gt_mcr.h"
> #include "xe_mmio.h"
> #include "xe_platform_types.h"
>+#include "xe_pm.h"
> #include "xe_sriov.h"
> #include "xe_step_types.h"
>
>@@ -36,6 +37,13 @@ struct xe_mocs_entry {
> u16 used;
> };
>
>+struct xe_mocs_info;
>+
>+struct xe_mocs_ops {
>+ void (*dump)(struct xe_mocs_info *mocs, unsigned int flags,
>+ struct xe_gt *gt, struct drm_printer *p);
>+};
>+
> struct xe_mocs_info {
> unsigned int size;
> unsigned int n_entries;
>@@ -43,6 +51,7 @@ struct xe_mocs_info {
> u8 uc_index;
> u8 wb_index;
> u8 unused_entries_index;
>+ const struct xe_mocs_ops *ops;
this creates a hole in the middle of the struct. Better move it near the
table member.
> };
>
> /* Defines for the tables (XXX_MOCS_0 - XXX_MOCS_63) */
>@@ -57,6 +66,17 @@ struct xe_mocs_info {
> #define LE_COS(value) ((value) << 15)
> #define LE_SSE(value) ((value) << 17)
>
>+#define LE_SSE_MASK REG_GENMASK(18, 17)
>+#define LE_COS_MASK REG_GENMASK(16, 15)
>+#define LE_SCF_MASK REG_BIT(14)
>+#define LE_PFM_MASK REG_GENMASK(13, 11)
>+#define LE_SCC_MASK REG_GENMASK(10, 8)
>+#define LE_RSC_MASK REG_BIT(7)
>+#define LE_AOM_MASK REG_BIT(6)
>+#define LE_LRUM_MASK REG_GENMASK(5, 4)
>+#define LE_TGT_CACHE_MASK REG_GENMASK(3, 2)
>+#define LE_CACHEABILITY_MASK REG_GENMASK(1, 0)
sorry for not noticing before: below I see you're doing:
reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_GLOBAL_MOCS(i));
or
reg_val = xe_mmio_read32(gt, XELP_GLOBAL_MOCS(i));
so these defines should be together with those registers in
drivers/gpu/drm/xe/regs/xe_gt_regs.h
>+
> /* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */
> #define L3_ESC(value) ((value) << 0)
> #define L3_SCC(value) ((value) << 1)
>@@ -64,6 +84,17 @@ struct xe_mocs_info {
> #define L3_GLBGO(value) ((value) << 6)
> #define L3_LKUP(value) ((value) << 7)
>
>+#define L3_UPPER_LKUP_MASK REG_BIT(23)
>+#define L3_UPPER_GLBGO_MASK REG_BIT(22)
>+#define L3_UPPER_IDX_CACHEABILITY_MASK REG_GENMASK(21, 20)
>+#define L3_UPPER_IDX_SCC_MASK REG_GENMASK(19, 17)
>+#define L3_UPPER_IDX_ESC_MASK REG_BIT(16)
>+#define L3_LKUP_MASK REG_BIT(7)
>+#define L3_GLBGO_MASK REG_BIT(6)
>+#define L3_CACHEABILITY_MASK REG_GENMASK(5, 4)
>+#define L3_SCC_MASK REG_GENMASK(3, 1)
>+#define L3_ESC_MASK REG_BIT(0)
ditto
>+
> /* Defines for the tables (GLOB_MOCS_0 - GLOB_MOCS_16) */
> #define IG_PAT REG_BIT(8)
> #define L3_CACHE_POLICY_MASK REG_GENMASK(5, 4)
>@@ -107,6 +138,8 @@ struct xe_mocs_info {
> #define XE2_L3_1_XD REG_FIELD_PREP(L3_CACHE_POLICY_MASK, 1)
> #define XE2_L3_3_UC REG_FIELD_PREP(L3_CACHE_POLICY_MASK, 3)
>
>+#define XE2_L3_CLOS_MASK REG_GENMASK(7, 6)
>+
> #define MOCS_ENTRY(__idx, __control_value, __l3cc_value) \
> [__idx] = { \
> .control_value = __control_value, \
>@@ -265,6 +298,74 @@ static bool regs_are_mcr(struct xe_gt *gt)
> return GRAPHICS_VERx100(xe) >= 1250;
> }
>
>+static void xelp_lncf_dump(struct xe_mocs_info *info, struct xe_gt *gt, struct drm_printer *p)
>+{
>+ unsigned int i, j;
>+ u32 reg_val;
>+
>+ drm_printf(p, "LNCFCMOCS[idx] = [ESC, SCC, L3CC] (value)\n\n");
>+
>+ for (i = 0, j = 0; i < (info->n_entries + 1) / 2; i++, j++) {
>+ if (regs_are_mcr(gt))
>+ reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_LNCFCMOCS(i));
>+ else
>+ reg_val = xe_mmio_read32(gt, XELP_LNCFCMOCS(i));
>+
>+ drm_printf(p, "LNCFCMOCS[%2d] = [%u, %u, %u] (%#8x)\n",
>+ j++,
>+ !!(reg_val & L3_ESC_MASK),
>+ REG_FIELD_GET(L3_SCC_MASK, reg_val),
>+ REG_FIELD_GET(L3_CACHEABILITY_MASK, reg_val),
>+ reg_val);
>+
>+ drm_printf(p, "LNCFCMOCS[%2d] = [%u, %u, %u] (%#8x)\n",
>+ j,
>+ !!(reg_val & L3_UPPER_IDX_ESC_MASK),
>+ REG_FIELD_GET(L3_UPPER_IDX_SCC_MASK, reg_val),
>+ REG_FIELD_GET(L3_UPPER_IDX_CACHEABILITY_MASK, reg_val),
>+ reg_val);
>+ }
>+}
>+
>+static void xelp_mocs_dump(struct xe_mocs_info *info, unsigned int flags,
>+ struct xe_gt *gt, struct drm_printer *p)
>+{
>+ unsigned int i;
>+ u32 reg_val;
>+
>+ if (flags & HAS_GLOBAL_MOCS) {
>+ drm_printf(p, "Global mocs table configuration:\n");
>+ drm_printf(p, "GLOB_MOCS[idx] = [LeCC, TC, LRUM, AOM, RSC, SCC, PFM, SCF, CoS, SSE] (value)\n\n");
>+
>+ for (i = 0; i < info->n_entries; i++) {
>+ if (regs_are_mcr(gt))
>+ reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_GLOBAL_MOCS(i));
>+ else
>+ reg_val = xe_mmio_read32(gt, XELP_GLOBAL_MOCS(i));
>+
>+ drm_printf(p, "GLOB_MOCS[%2d] = [%u, %u, %u, %u, %u, %u, %u, %u, %u, %u ] (%#8x)\n",
indentation here is misleading
>+ i,
>+ REG_FIELD_GET(LE_CACHEABILITY_MASK, reg_val),
>+ REG_FIELD_GET(LE_TGT_CACHE_MASK, reg_val),
>+ REG_FIELD_GET(LE_LRUM_MASK, reg_val),
>+ !!(reg_val & LE_AOM_MASK),
>+ !!(reg_val & LE_RSC_MASK),
>+ REG_FIELD_GET(LE_SCC_MASK, reg_val),
>+ REG_FIELD_GET(LE_PFM_MASK, reg_val),
>+ !!(reg_val & LE_SCF_MASK),
>+ REG_FIELD_GET(LE_COS_MASK, reg_val),
>+ REG_FIELD_GET(LE_SSE_MASK, reg_val),
>+ reg_val);
>+ }
>+ }
>+
>+ xelp_lncf_dump(info, gt, p);
>+}
>+
>+static const struct xe_mocs_ops xelp_mocs_ops = {
>+ .dump = xelp_mocs_dump,
>+};
>+
> static const struct xe_mocs_entry dg1_mocs_desc[] = {
> /* UC */
> MOCS_ENTRY(1, 0, L3_1_UC),
>@@ -301,6 +402,40 @@ static const struct xe_mocs_entry dg2_mocs_desc[] = {
> MOCS_ENTRY(3, 0, L3_3_WB | L3_LKUP(1)),
> };
>
>+static void xehp_lncf_dump(struct xe_mocs_info *info, unsigned int flags,
>+ struct xe_gt *gt, struct drm_printer *p)
>+{
>+ unsigned int i, j;
>+ u32 reg_val;
>+
>+ drm_printf(p, "LNCFCMOCS[idx] = [UCL3LOOKUP, GLBGO, L3CC] (value)\n\n");
>+
>+ for (i = 0, j = 0; i < (info->n_entries + 1) / 2; i++, j++) {
>+ if (regs_are_mcr(gt))
>+ reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_LNCFCMOCS(i));
>+ else
>+ reg_val = xe_mmio_read32(gt, XELP_LNCFCMOCS(i));
>+
>+ drm_printf(p, "LNCFCMOCS[%2d] = [%u, %u, %u] (%#8x)\n",
>+ j++,
>+ !!(reg_val & L3_LKUP_MASK),
>+ !!(reg_val & L3_GLBGO_MASK),
>+ REG_FIELD_GET(L3_CACHEABILITY_MASK, reg_val),
>+ reg_val);
>+
>+ drm_printf(p, "LNCFCMOCS[%2d] = [%u, %u, %u] (%#8x)\n",
>+ j,
>+ !!(reg_val & L3_UPPER_LKUP_MASK),
>+ !!(reg_val & L3_UPPER_GLBGO_MASK),
>+ REG_FIELD_GET(L3_UPPER_IDX_CACHEABILITY_MASK, reg_val),
>+ reg_val);
>+ }
>+}
>+
>+static const struct xe_mocs_ops xehp_mocs_ops = {
>+ .dump = xehp_lncf_dump,
>+};
>+
> static const struct xe_mocs_entry pvc_mocs_desc[] = {
> /* Error */
> MOCS_ENTRY(0, 0, L3_3_WB),
>@@ -312,6 +447,36 @@ static const struct xe_mocs_entry pvc_mocs_desc[] = {
> MOCS_ENTRY(2, 0, L3_3_WB),
> };
>
>+static void pvc_mocs_dump(struct xe_mocs_info *info, unsigned int flags, struct xe_gt *gt,
>+ struct drm_printer *p)
>+{
>+ unsigned int i, j;
>+ u32 reg_val;
>+
>+ drm_printf(p, "LNCFCMOCS[idx] = [ L3CC ] (value)\n\n");
>+
>+ for (i = 0, j = 0; i < (info->n_entries + 1) / 2; i++, j++) {
>+ if (regs_are_mcr(gt))
>+ reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_LNCFCMOCS(i));
>+ else
>+ reg_val = xe_mmio_read32(gt, XELP_LNCFCMOCS(i));
>+
>+ drm_printf(p, "LNCFCMOCS[%2d] = [ %u ] (%#8x)\n",
>+ j++,
>+ REG_FIELD_GET(L3_CACHEABILITY_MASK, reg_val),
>+ reg_val);
>+
>+ drm_printf(p, "LNCFCMOCS[%2d] = [ %u ] (%#8x)\n",
>+ j,
>+ REG_FIELD_GET(L3_UPPER_IDX_CACHEABILITY_MASK, reg_val),
>+ reg_val);
>+ }
>+}
>+
>+static const struct xe_mocs_ops pvc_mocs_ops = {
>+ .dump = pvc_mocs_dump,
>+};
>+
> static const struct xe_mocs_entry mtl_mocs_desc[] = {
> /* Error - Reserved for Non-Use */
> MOCS_ENTRY(0,
>@@ -363,6 +528,36 @@ static const struct xe_mocs_entry mtl_mocs_desc[] = {
> L3_GLBGO(1) | L3_1_UC),
> };
>
>+static void mtl_mocs_dump(struct xe_mocs_info *info, unsigned int flags,
>+ struct xe_gt *gt, struct drm_printer *p)
>+{
>+ unsigned int i;
>+ u32 reg_val;
>+
>+ drm_printf(p, "Global mocs table configuration:\n");
>+ drm_printf(p, "GLOB_MOCS[idx] = [IG_PAT, L4_CACHE_POLICY] (value)\n\n");
>+
>+ for (i = 0; i < info->n_entries; i++) {
>+ if (regs_are_mcr(gt))
>+ reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_GLOBAL_MOCS(i));
>+ else
>+ reg_val = xe_mmio_read32(gt, XELP_GLOBAL_MOCS(i));
>+
>+ drm_printf(p, "GLOB_MOCS[%2d] = [%u, %u] (%#8x)\n",
>+ i,
>+ !!(reg_val & IG_PAT),
>+ REG_FIELD_GET(L4_CACHE_POLICY_MASK, reg_val),
>+ reg_val);
>+ }
>+
>+ /* MTL lncf mocs table pattern is similar to that of xehp */
>+ xehp_lncf_dump(info, flags, gt, p);
>+}
>+
>+static const struct xe_mocs_ops mtl_mocs_ops = {
>+ .dump = mtl_mocs_dump,
>+};
>+
> static const struct xe_mocs_entry xe2_mocs_table[] = {
> /* Defer to PAT */
> MOCS_ENTRY(0, XE2_L3_0_WB | L4_3_UC, 0),
>@@ -376,6 +571,34 @@ static const struct xe_mocs_entry xe2_mocs_table[] = {
> MOCS_ENTRY(4, IG_PAT | XE2_L3_0_WB | L4_0_WB, 0),
> };
>
>+static void xe2_mocs_dump(struct xe_mocs_info *info, unsigned int flags,
>+ struct xe_gt *gt, struct drm_printer *p)
>+{
>+ unsigned int i;
>+ u32 reg_val;
>+
>+ drm_printf(p, "Global mocs table configuration:\n");
>+ drm_printf(p, "GLOB_MOCS[idx] = [IG_PAT, L3_CLOS, L3_CACHE_POLICY, L4_CACHE_POLICY] (value)\n\n");
>+
>+ for (i = 0; i < info->n_entries; i++) {
>+ if (regs_are_mcr(gt))
>+ reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_GLOBAL_MOCS(i));
>+ else
>+ reg_val = xe_mmio_read32(gt, XELP_GLOBAL_MOCS(i));
>+
>+ drm_printf(p, "GLOB_MOCS[%2d] = [%u, %u, %u] (%#8x)\n",
>+ i,
>+ !!(reg_val & IG_PAT),
>+ REG_FIELD_GET(XE2_L3_CLOS_MASK, reg_val),
>+ REG_FIELD_GET(L4_CACHE_POLICY_MASK, reg_val),
>+ reg_val);
>+ }
>+}
>+
>+static const struct xe_mocs_ops xe2_mocs_ops = {
>+ .dump = xe2_mocs_dump,
>+};
>+
> static unsigned int get_mocs_settings(struct xe_device *xe,
> struct xe_mocs_info *info)
> {
>@@ -386,6 +609,7 @@ static unsigned int get_mocs_settings(struct xe_device *xe,
this get_mocs_settings being called over and over: we may need to
redesign it, but no need to worry for now.
rest looks correct so next version we should hopefully be able to apply.
Please confirm the platforms this was tested on.
Below is a (untested) diff with part of the things I mentioned. Feel
free to use it to squash the changes.
|diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
|index 83847f2da72a..8f44437c8e02 100644
|--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
|+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
|@@ -59,6 +59,27 @@
|
| #define XELP_GLOBAL_MOCS(i) XE_REG(0x4000 + (i) * 4)
| #define XEHP_GLOBAL_MOCS(i) XE_REG_MCR(0x4000 + (i) * 4)
|+#define LE_SSE_MASK REG_GENMASK(18, 17)
|+#define LE_SSE(value) REG_FIELD_PREP(LE_SSE_MASK, value)
|+#define LE_COS_MASK REG_GENMASK(16, 15)
|+#define LE_COS(value) REG_FIELD_PREP(LE_COS_MASK)
|+#define LE_SCF_MASK REG_BIT(14)
|+#define LE_SCF(value) REG_FIELD_PREP(LE_SCF_MASK, value)
|+#define LE_PFM_MASK REG_GENMASK(13, 11)
|+#define LE_PFM(value) REG_FIELD_PREP(LE_PFM_MASK, value)
|+#define LE_SCC_MASK REG_GENMASK(10, 8)
|+#define LE_SCC(value) REG_FIELD_PREP(LE_SCC_MASK, value)
|+#define LE_RSC_MASK REG_BIT(7)
|+#define LE_RSC(value) REG_FIELD_PREP(LE_RSC_MASK, value)
|+#define LE_AOM_MASK REG_BIT(6)
|+#define LE_AOM(value) REG_FIELD_PREP(LE_AOM_MASK, value)
|+#define LE_LRUM_MASK REG_GENMASK(5, 4)
|+#define LE_LRUM(value) REG_FIELD_PREP(LE_LRUM_MASK, value)
|+#define LE_TGT_CACHE_MASK REG_GENMASK(3, 2)
|+#define LE_TGT_CACHE(value) REG_FIELD_PREP(LE_TGT_CACHE_MASK, value)
|+#define LE_CACHEABILITY_MASK REG_GENMASK(1, 0)
|+#define LE_CACHEABILITY(value) REG_FIELD_PREP(LE_CACHEABILITY_MASK, value)
|+
| #define CCS_AUX_INV XE_REG(0x4208)
|
| #define VD0_AUX_INV XE_REG(0x4218)
|@@ -314,9 +335,24 @@
| #define XEHPC_OVRLSCCC REG_BIT(0)
|
| /* L3 Cache Control */
|+#define LNCFCMOCS_REG_COUNT 32
| #define XELP_LNCFCMOCS(i) XE_REG(0xb020 + (i) * 4)
| #define XEHP_LNCFCMOCS(i) XE_REG_MCR(0xb020 + (i) * 4)
|-#define LNCFCMOCS_REG_COUNT 32
|+#define L3_UPPER_LKUP_MASK REG_BIT(23)
|+#define L3_UPPER_GLBGO_MASK REG_BIT(22)
|+#define L3_UPPER_IDX_CACHEABILITY_MASK REG_GENMASK(21, 20)
|+#define L3_UPPER_IDX_SCC_MASK REG_GENMASK(19, 17)
|+#define L3_UPPER_IDX_ESC_MASK REG_BIT(16)
|+#define L3_LKUP_MASK REG_BIT(7)
|+#define L3_LKUP(value) REG_FIELD_PREP(L3_LKUP_MASK, value)
|+#define L3_GLBGO_MASK REG_BIT(6)
|+#define L3_GLBGO(value) REG_FIELD_PREP(L3_GLBGO_MASK, value)
|+#define L3_CACHEABILITY_MASK REG_GENMASK(5, 4)
|+#define L3_CACHEABILITY(value) REG_FIELD_PREP(L3_CACHEABILITY_MASK, value)
|+#define L3_SCC_MASK REG_GENMASK(3, 1)
|+#define L3_SCC(value) REG_FIELD_PREP(L3_SCC_MASK, value)
|+#define L3_ESC_MASK REG_BIT(0)
|+#define L3_ESC(value) REG_FIELD_PREP(L3_ESC_MASK, value)
|
| #define XEHP_L3NODEARBCFG XE_REG_MCR(0xb0b4)
| #define XEHP_LNESPARE REG_BIT(19)
|diff --git a/drivers/gpu/drm/xe/xe_mocs.c b/drivers/gpu/drm/xe/xe_mocs.c
|index a7caa9df0470..7c75b827cb82 100644
|--- a/drivers/gpu/drm/xe/xe_mocs.c
|+++ b/drivers/gpu/drm/xe/xe_mocs.c
|@@ -48,53 +48,12 @@ struct xe_mocs_info {
| unsigned int size;
| unsigned int n_entries;
| const struct xe_mocs_entry *table;
|+ const struct xe_mocs_ops *ops;
| u8 uc_index;
| u8 wb_index;
| u8 unused_entries_index;
|- const struct xe_mocs_ops *ops;
| };
|
|-/* Defines for the tables (XXX_MOCS_0 - XXX_MOCS_63) */
|-#define _LE_CACHEABILITY(value) ((value) << 0)
|-#define _LE_TGT_CACHE(value) ((value) << 2)
|-#define LE_LRUM(value) ((value) << 4)
|-#define LE_AOM(value) ((value) << 6)
|-#define LE_RSC(value) ((value) << 7)
|-#define LE_SCC(value) ((value) << 8)
|-#define LE_PFM(value) ((value) << 11)
|-#define LE_SCF(value) ((value) << 14)
|-#define LE_COS(value) ((value) << 15)
|-#define LE_SSE(value) ((value) << 17)
|-
|-#define LE_SSE_MASK REG_GENMASK(18, 17)
|-#define LE_COS_MASK REG_GENMASK(16, 15)
|-#define LE_SCF_MASK REG_BIT(14)
|-#define LE_PFM_MASK REG_GENMASK(13, 11)
|-#define LE_SCC_MASK REG_GENMASK(10, 8)
|-#define LE_RSC_MASK REG_BIT(7)
|-#define LE_AOM_MASK REG_BIT(6)
|-#define LE_LRUM_MASK REG_GENMASK(5, 4)
|-#define LE_TGT_CACHE_MASK REG_GENMASK(3, 2)
|-#define LE_CACHEABILITY_MASK REG_GENMASK(1, 0)
|-
|-/* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */
|-#define L3_ESC(value) ((value) << 0)
|-#define L3_SCC(value) ((value) << 1)
|-#define _L3_CACHEABILITY(value) ((value) << 4)
|-#define L3_GLBGO(value) ((value) << 6)
|-#define L3_LKUP(value) ((value) << 7)
|-
|-#define L3_UPPER_LKUP_MASK REG_BIT(23)
|-#define L3_UPPER_GLBGO_MASK REG_BIT(22)
|-#define L3_UPPER_IDX_CACHEABILITY_MASK REG_GENMASK(21, 20)
|-#define L3_UPPER_IDX_SCC_MASK REG_GENMASK(19, 17)
|-#define L3_UPPER_IDX_ESC_MASK REG_BIT(16)
|-#define L3_LKUP_MASK REG_BIT(7)
|-#define L3_GLBGO_MASK REG_BIT(6)
|-#define L3_CACHEABILITY_MASK REG_GENMASK(5, 4)
|-#define L3_SCC_MASK REG_GENMASK(3, 1)
|-#define L3_ESC_MASK REG_BIT(0)
|-
| /* Defines for the tables (GLOB_MOCS_0 - GLOB_MOCS_16) */
| #define IG_PAT REG_BIT(8)
| #define L3_CACHE_POLICY_MASK REG_GENMASK(5, 4)
|@@ -111,22 +70,20 @@ struct xe_mocs_info {
| * Note: LE_0_PAGETABLE works only up to Gen11; for newer gens it means
| * the same as LE_UC
| */
|-#define LE_0_PAGETABLE _LE_CACHEABILITY(0)
|-#define LE_1_UC _LE_CACHEABILITY(1)
|-#define LE_2_WT _LE_CACHEABILITY(2)
|-#define LE_3_WB _LE_CACHEABILITY(3)
|+#define LE_1_UC LE_CACHEABILITY(1)
|+#define LE_2_WT LE_CACHEABILITY(2)
|+#define LE_3_WB LE_CACHEABILITY(3)
|
| /* Target cache */
|-#define LE_TC_0_PAGETABLE _LE_TGT_CACHE(0)
|-#define LE_TC_1_LLC _LE_TGT_CACHE(1)
|-#define LE_TC_2_LLC_ELLC _LE_TGT_CACHE(2)
|-#define LE_TC_3_LLC_ELLC_ALT _LE_TGT_CACHE(3)
|+#define LE_TC_1_LLC LE_TGT_CACHE(1)
|+#define LE_TC_2_LLC_ELLC LE_TGT_CACHE(2)
|+#define LE_TC_3_LLC_ELLC_ALT LE_TGT_CACHE(3)
|
| /* L3 caching options */
|-#define L3_0_DIRECT _L3_CACHEABILITY(0)
|-#define L3_1_UC _L3_CACHEABILITY(1)
|-#define L3_2_RESERVED _L3_CACHEABILITY(2)
|-#define L3_3_WB _L3_CACHEABILITY(3)
|+#define L3_0_DIRECT L3_CACHEABILITY(0)
|+#define L3_1_UC L3_CACHEABILITY(1)
|+#define L3_2_RESERVED L3_CACHEABILITY(2)
|+#define L3_3_WB L3_CACHEABILITY(3)
|
| /* L4 caching options */
| #define L4_0_WB REG_FIELD_PREP(L4_CACHE_POLICY_MASK, 0)
thanks
Lucas De Marchi
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