[PATCH v2] drm/xe/xe2: Add workaround 14021402888

[Bommu, Krishnaiah]

> -----Original Message-----
> From: De Marchi, Lucas <lucas.demarchi at intel.com>
> Sent: Tuesday, April 30, 2024 8:13 PM
> To: Bommu, Krishnaiah <krishnaiah.bommu at intel.com>
> Cc: intel-xe at lists.freedesktop.org; Upadhyay, Tejas
> <tejas.upadhyay at intel.com>; Roper, Matthew D
> <matthew.d.roper at intel.com>; Ghimiray, Himal Prasad
> <himal.prasad.ghimiray at intel.com>
> Subject: Re: [PATCH v2] drm/xe/xe2: Add workaround 14021402888
> 
> On Thu, Apr 18, 2024 at 04:45:34PM GMT, Bommu Krishnaiah wrote:
> >This workaround applies to Graphics 20.01 as RCS engine workaround
> >
> >Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu at intel.com>
> >Cc: Tejas Upadhyay <tejas.upadhyay at intel.com>
> >Cc: Matt Roper <matthew.d.roper at intel.com>
> >Cc: Himal Prasad Ghimiray <himal.prasad.ghimiray at intel.com>
> >---
> > drivers/gpu/drm/xe/regs/xe_gt_regs.h | 1 +
> > drivers/gpu/drm/xe/xe_wa.c           | 4 ++++
> > 2 files changed, 5 insertions(+)
> >
> >diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> >b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> >index 94445810ccc9..23c302af4cd5 100644
> >--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> >+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> >@@ -350,6 +350,7 @@
> >
> > #define HALF_SLICE_CHICKEN7
> 	XE_REG_MCR(0xe194, XE_REG_OPTION_MASKED)
> > #define   DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA	REG_BIT(15)
> >+#define   CLEAR_OPTIMIZATION_DISABLE			REG_BIT(6)
> >
> > #define CACHE_MODE_SS				XE_REG_MCR(0xe420,
> XE_REG_OPTION_MASKED)
> > #define   DISABLE_ECC				REG_BIT(5)
> >diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
> >index 632bd9066f8d..31e140968f4a 100644
> >--- a/drivers/gpu/drm/xe/xe_wa.c
> >+++ b/drivers/gpu/drm/xe/xe_wa.c
> >@@ -534,6 +534,10 @@ static const struct xe_rtp_entry_sr engine_was[] = {
> > 		       FUNC(xe_rtp_match_first_render_or_compute)),
> > 	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0,
> WR_REQ_CHAINING_DIS))
> > 	},
> >+	{ XE_RTP_NAME("14021402888"),
> >+	  XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
> 
> we don't have BMG in CI so we have to be cautious on applying WAs. We had
> cases that we merged it just to realize the WA was not really working. Did you
> check the WA is applying correctly?

I validated this changes on BMG before sending. Device boots properly and sysfs node shows this wa applied too

Regards,
Krishna.
> 
> Lucas De Marchi
> 
> >+	  XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7,
> CLEAR_OPTIMIZATION_DISABLE))
> >+	},
> >
> > 	/* Xe2_HPM */
> >
> >--
> >2.25.1
> >