[PATCH 3/4] drm/xe: Dump Indirect Ring State registers

[Summers, Stuart]

On Sat, 2024-05-04 at 16:35 -0700, Niranjana Vishwanathapura wrote:
> Dump INDIRECT_RING_STATE and RING_START_UDW registers.
> 
> Signed-off-by: Niranjana Vishwanathapura
> <niranjana.vishwanathapura at intel.com>

Reviewed-by: Stuart Summers <stuart.summers at intel.com>

> ---
>  drivers/gpu/drm/xe/regs/xe_engine_regs.h |  4 ++++
>  drivers/gpu/drm/xe/xe_hw_engine.c        | 11 +++++++++++
>  drivers/gpu/drm/xe/xe_hw_engine_types.h  |  4 ++++
>  3 files changed, 19 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> index 260a44f46f7e..263ffc7bc2ef 100644
> --- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> @@ -55,6 +55,8 @@
>  #define   RING_CTL_SIZE(size)                  ((size) - PAGE_SIZE)
> /* in bytes -> pages */
>  #define   RING_CTL_SIZE(size)                  ((size) - PAGE_SIZE)
> /* in bytes -> pages */
>  
> +#define RING_START_UDW(base)                   XE_REG((base) + 0x48)
> +
>  #define RING_PSMI_CTL(base)                    XE_REG((base) + 0x50,
> XE_REG_OPTION_MASKED)
>  #define   RC_SEMA_IDLE_MSG_DISABLE             REG_BIT(12)
>  #define   WAIT_FOR_EVENT_POWER_DOWN_DISABLE    REG_BIT(7)
> @@ -110,6 +112,8 @@
>  #define   FF_DOP_CLOCK_GATE_DISABLE            REG_BIT(1)
>  #define   REPLAY_MODE_GRANULARITY              REG_BIT(0)
>  
> +#define INDIRECT_RING_STATE(base)              XE_REG((base) +
> 0x108)
> +
>  #define RING_BBADDR(base)                      XE_REG((base) +
> 0x140)
>  #define RING_BBADDR_UDW(base)                  XE_REG((base) +
> 0x168)
>  
> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c
> b/drivers/gpu/drm/xe/xe_hw_engine.c
> index ec69803152a2..45f582a7caaa 100644
> --- a/drivers/gpu/drm/xe/xe_hw_engine.c
> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
> @@ -908,6 +908,13 @@ xe_hw_engine_snapshot_capture(struct
> xe_hw_engine *hwe)
>         snapshot->reg.ring_hwstam = hw_engine_mmio_read32(hwe,
> RING_HWSTAM(0));
>         snapshot->reg.ring_hws_pga = hw_engine_mmio_read32(hwe,
> RING_HWS_PGA(0));
>         snapshot->reg.ring_start = hw_engine_mmio_read32(hwe,
> RING_START(0));
> +       if (xe_gt_has_indirect_ring_state(hwe->gt)) {
> +               snapshot->reg.indirect_ring_state =
> +                       hw_engine_mmio_read32(hwe,
> INDIRECT_RING_STATE(0));
> +               snapshot->reg.ring_start_udw =
> +                       hw_engine_mmio_read32(hwe,
> RING_START_UDW(0));
> +       }
> +
>         snapshot->reg.ring_head =
>                 hw_engine_mmio_read32(hwe, RING_HEAD(0)) & HEAD_ADDR;
>         snapshot->reg.ring_tail =
> @@ -997,6 +1004,8 @@ void xe_hw_engine_snapshot_print(struct
> xe_hw_engine_snapshot *snapshot,
>         drm_printf(p, "\tRING_EXECLIST_SQ_CONTENTS: 0x%016llx\n",
>                    snapshot->reg.ring_execlist_sq_contents);
>         drm_printf(p, "\tRING_START: 0x%08x\n", snapshot-
> >reg.ring_start);
> +       drm_printf(p, "\tRING_START_UDW: 0x%08x\n",
> +                  snapshot->reg.ring_start_udw);
>         drm_printf(p, "\tRING_HEAD: 0x%08x\n", snapshot-
> >reg.ring_head);
>         drm_printf(p, "\tRING_TAIL: 0x%08x\n", snapshot-
> >reg.ring_tail);
>         drm_printf(p, "\tRING_CTL: 0x%08x\n", snapshot-
> >reg.ring_ctl);
> @@ -1010,6 +1019,8 @@ void xe_hw_engine_snapshot_print(struct
> xe_hw_engine_snapshot *snapshot,
>         drm_printf(p, "\tACTHD: 0x%016llx\n", snapshot-
> >reg.ring_acthd);
>         drm_printf(p, "\tBBADDR: 0x%016llx\n", snapshot-
> >reg.ring_bbaddr);
>         drm_printf(p, "\tDMA_FADDR: 0x%016llx\n", snapshot-
> >reg.ring_dma_fadd);
> +       drm_printf(p, "\tINDIRECT_RING_STATE: 0x%08x\n",
> +                  snapshot->reg.indirect_ring_state);
>         drm_printf(p, "\tIPEHR: 0x%08x\n", snapshot->reg.ipehr);
>         xe_hw_engine_snapshot_instdone_print(snapshot, p);
>  
> diff --git a/drivers/gpu/drm/xe/xe_hw_engine_types.h
> b/drivers/gpu/drm/xe/xe_hw_engine_types.h
> index 9f9755e31b9f..5f4b67acba99 100644
> --- a/drivers/gpu/drm/xe/xe_hw_engine_types.h
> +++ b/drivers/gpu/drm/xe/xe_hw_engine_types.h
> @@ -189,6 +189,8 @@ struct xe_hw_engine_snapshot {
>                 u32 ring_hws_pga;
>                 /** @reg.ring_start: RING_START */
>                 u32 ring_start;
> +               /** @reg.ring_start_udw: RING_START_UDW */
> +               u32 ring_start_udw;
>                 /** @reg.ring_head: RING_HEAD */
>                 u32 ring_head;
>                 /** @reg.ring_tail: RING_TAIL */
> @@ -207,6 +209,8 @@ struct xe_hw_engine_snapshot {
>                 u32 ring_emr;
>                 /** @reg.ring_eir: RING_EIR */
>                 u32 ring_eir;
> +               /** @reg.indirect_ring_state: INDIRECT_RING_STATE */
> +               u32 indirect_ring_state;
>                 /** @reg.ipehr: IPEHR */
>                 u32 ipehr;
>                 /** @reg.rcu_mode: RCU_MODE */