[PATCH 0/2] Enable Coarse Power Gating

Riana Tauro riana.tauro at intel.com
Tue May 14 06:43:07 UTC 2024


Coarse Power Gating (CPG), where Render and Media can enter C6
independent of the remaining GT. Enable render and media
power gating

Also enable VD HCP/MFX sub-pipe power gating
HCP/MFX power gating is disabled by default, turn it on for
the vd units available.

Riana Tauro (2):
  drm/xe: change the power gating register names
  RFC drm/xe: Enable Coarse Power Gating

 drivers/gpu/drm/xe/regs/xe_gt_regs.h | 10 +++----
 drivers/gpu/drm/xe/xe_gt.c           | 10 +++++++
 drivers/gpu/drm/xe/xe_gt_idle.c      | 45 ++++++++++++++++++++++++++--
 drivers/gpu/drm/xe/xe_gt_idle.h      |  2 ++
 drivers/gpu/drm/xe/xe_wa.c           | 10 +++----
 5 files changed, 64 insertions(+), 13 deletions(-)

-- 
2.40.0



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