✓ CI.checkpatch: success for Enable Coarse Power Gating

[Patchwork]

== Series Details ==

Series: Enable Coarse Power Gating
URL   : https://patchwork.freedesktop.org/series/133582/
State : success

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
57b97a66dd129aea93991dc66cd10477f7a05cf8
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 6989e7a19feb4ab2ab9bebc87cd3d47e6c31dd35
Author: Riana Tauro <riana.tauro at intel.com>
Date:   Tue May 14 12:13:09 2024 +0530

    RFC drm/xe: Enable Coarse Power Gating
    
    Coarse Power Gating (CPG), where Render and Media can enter C6
    independent of the remaining GT. Enable render and media
    power gating.
    
    Also enable VD HCP/MFX sub-pipe power gating.
    HCP/MFX power gating is disabled by default, turn it on for
    the vd units available
    
    Signed-off-by: Riana Tauro <riana.tauro at intel.com>
+ /mt/dim checkpatch 90004c84ff25805007de766bf47ba255e4a0d9f2 drm-intel
969c9df22a5f drm/xe: change the power gating register names
6989e7a19feb RFC drm/xe: Enable Coarse Power Gating