[PATCH v4 3/8] drm/xe/lrc: Add helper to capture context timestamp
Francois Dugast
francois.dugast at intel.com
Fri May 17 16:39:42 UTC 2024
On Wed, May 15, 2024 at 02:42:53PM -0700, Lucas De Marchi wrote:
> From: Umesh Nerlige Ramappa <umesh.nerlige.ramappa at intel.com>
>
> Add a helper to capture CTX_TIMESTAMP from the context image so it can
> be used to calculate the runtime.
>
> v2: Add kernel-doc to clarify expectation from caller
>
> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa at intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
LGTM:
Reviewed-by: Francois Dugast <francois.dugast at intel.com>
> ---
> drivers/gpu/drm/xe/regs/xe_lrc_layout.h | 1 +
> drivers/gpu/drm/xe/xe_lrc.c | 12 ++++++++++++
> drivers/gpu/drm/xe/xe_lrc.h | 14 ++++++++++++++
> drivers/gpu/drm/xe/xe_lrc_types.h | 3 +++
> 4 files changed, 30 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_lrc_layout.h b/drivers/gpu/drm/xe/regs/xe_lrc_layout.h
> index e6ca8bbda8f4..045dfd09db99 100644
> --- a/drivers/gpu/drm/xe/regs/xe_lrc_layout.h
> +++ b/drivers/gpu/drm/xe/regs/xe_lrc_layout.h
> @@ -11,6 +11,7 @@
> #define CTX_RING_TAIL (0x06 + 1)
> #define CTX_RING_START (0x08 + 1)
> #define CTX_RING_CTL (0x0a + 1)
> +#define CTX_TIMESTAMP (0x22 + 1)
> #define CTX_INDIRECT_RING_STATE (0x26 + 1)
> #define CTX_PDP0_UDW (0x30 + 1)
> #define CTX_PDP0_LDW (0x32 + 1)
> diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
> index 9b0a4078add3..f679cb9aaea7 100644
> --- a/drivers/gpu/drm/xe/xe_lrc.c
> +++ b/drivers/gpu/drm/xe/xe_lrc.c
> @@ -844,6 +844,7 @@ int xe_lrc_init(struct xe_lrc *lrc, struct xe_hw_engine *hwe,
> lrc->tile = gt_to_tile(hwe->gt);
> lrc->ring.size = ring_size;
> lrc->ring.tail = 0;
> + lrc->ctx_timestamp = 0;
>
> xe_hw_fence_ctx_init(&lrc->fence_ctx, hwe->gt,
> hwe->fence_irq, hwe->name);
> @@ -898,6 +899,8 @@ int xe_lrc_init(struct xe_lrc *lrc, struct xe_hw_engine *hwe,
> RING_CTL_SIZE(lrc->ring.size) | RING_VALID);
> }
>
> + xe_lrc_write_ctx_reg(lrc, CTX_TIMESTAMP, 0);
> +
> if (xe->info.has_asid && vm)
> xe_lrc_write_ctx_reg(lrc, PVC_CTX_ASID, vm->usm.asid);
>
> @@ -1576,3 +1579,12 @@ void xe_lrc_snapshot_free(struct xe_lrc_snapshot *snapshot)
> xe_bo_put(snapshot->lrc_bo);
> kfree(snapshot);
> }
> +
> +u32 xe_lrc_update_timestamp(struct xe_lrc *lrc, u32 *old_ts)
> +{
> + *old_ts = lrc->ctx_timestamp;
> +
> + lrc->ctx_timestamp = xe_lrc_read_ctx_reg(lrc, CTX_TIMESTAMP);
> +
> + return lrc->ctx_timestamp;
> +}
> diff --git a/drivers/gpu/drm/xe/xe_lrc.h b/drivers/gpu/drm/xe/xe_lrc.h
> index e0e841963c23..b9da1031083b 100644
> --- a/drivers/gpu/drm/xe/xe_lrc.h
> +++ b/drivers/gpu/drm/xe/xe_lrc.h
> @@ -66,4 +66,18 @@ void xe_lrc_snapshot_capture_delayed(struct xe_lrc_snapshot *snapshot);
> void xe_lrc_snapshot_print(struct xe_lrc_snapshot *snapshot, struct drm_printer *p);
> void xe_lrc_snapshot_free(struct xe_lrc_snapshot *snapshot);
>
> +/**
> + * xe_lrc_update_timestamp - readout LRC timestamp and update cached value
> + * @lrc: logical ring context for this exec queue
> + * @old_ts: pointer where to save the previous timestamp
> + *
> + * Read the current timestamp for this LRC and update the cached value. The
> + * previous cached value is also returned in @old_ts so the caller can calculate
> + * the delta between 2 updates. Note that this is not intended to be called from
> + * any place, but just by the paths updating the drm client utilization.
> + *
> + * Returns the current LRC timestamp
> + */
> +u32 xe_lrc_update_timestamp(struct xe_lrc *lrc, u32 *old_ts);
> +
> #endif
> diff --git a/drivers/gpu/drm/xe/xe_lrc_types.h b/drivers/gpu/drm/xe/xe_lrc_types.h
> index cdbf03faef15..0fa055da6b27 100644
> --- a/drivers/gpu/drm/xe/xe_lrc_types.h
> +++ b/drivers/gpu/drm/xe/xe_lrc_types.h
> @@ -45,6 +45,9 @@ struct xe_lrc {
>
> /** @fence_ctx: context for hw fence */
> struct xe_hw_fence_ctx fence_ctx;
> +
> + /** @ctx_timestamp: readout value of CTX_TIMESTAMP on last update */
> + u32 ctx_timestamp;
> };
>
> struct xe_lrc_snapshot;
> --
> 2.43.0
>
More information about the Intel-xe
mailing list