[PATCH] drm/xe: Replace RING_START_UDW by u64 RING_START

[Niranjana Vishwanathapura]

On Fri, May 10, 2024 at 08:01:08AM -0700, José Roberto de Souza wrote:
>Other u64 registers are printed in a single line so RING_START
>needs to follow that too.
>As there is no upstream decoder tool parsing RING_START this will
>not break any decoder application.
>
>Cc: Niranjana Vishwanathapura <niranjana.vishwanathapura at intel.com>
>Cc: Matt Roper <matthew.d.roper at intel.com>
>Signed-off-by: José Roberto de Souza <jose.souza at intel.com>
>---
> drivers/gpu/drm/xe/xe_hw_engine.c       | 10 +++++-----
> drivers/gpu/drm/xe/xe_hw_engine_types.h |  4 +---
> 2 files changed, 6 insertions(+), 8 deletions(-)
>
>diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
>index 45f582a7caaa5..e19af179af338 100644
>--- a/drivers/gpu/drm/xe/xe_hw_engine.c
>+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
>@@ -908,11 +908,13 @@ xe_hw_engine_snapshot_capture(struct xe_hw_engine *hwe)
> 	snapshot->reg.ring_hwstam = hw_engine_mmio_read32(hwe, RING_HWSTAM(0));
> 	snapshot->reg.ring_hws_pga = hw_engine_mmio_read32(hwe, RING_HWS_PGA(0));
> 	snapshot->reg.ring_start = hw_engine_mmio_read32(hwe, RING_START(0));
>+	if (GRAPHICS_VERx100(hwe->gt->tile->xe) >= 2000) {
>+		val = hw_engine_mmio_read32(hwe, RING_START_UDW(0));
>+		snapshot->reg.ring_start |= val << 32;
>+	}
> 	if (xe_gt_has_indirect_ring_state(hwe->gt)) {
> 		snapshot->reg.indirect_ring_state =
> 			hw_engine_mmio_read32(hwe, INDIRECT_RING_STATE(0));
>-		snapshot->reg.ring_start_udw =
>-			hw_engine_mmio_read32(hwe, RING_START_UDW(0));
> 	}

I think the braces can be removed here as there is only one statement now.
Other than that,

Reviewed-by: Niranjana Vishwanathapura <niranjana.vishwanathapura at intel.com>

>
> 	snapshot->reg.ring_head =
>@@ -1003,9 +1005,7 @@ void xe_hw_engine_snapshot_print(struct xe_hw_engine_snapshot *snapshot,
> 		   snapshot->reg.ring_execlist_status);
> 	drm_printf(p, "\tRING_EXECLIST_SQ_CONTENTS: 0x%016llx\n",
> 		   snapshot->reg.ring_execlist_sq_contents);
>-	drm_printf(p, "\tRING_START: 0x%08x\n", snapshot->reg.ring_start);
>-	drm_printf(p, "\tRING_START_UDW: 0x%08x\n",
>-		   snapshot->reg.ring_start_udw);
>+	drm_printf(p, "\tRING_START: 0x%016llx\n", snapshot->reg.ring_start);
> 	drm_printf(p, "\tRING_HEAD: 0x%08x\n", snapshot->reg.ring_head);
> 	drm_printf(p, "\tRING_TAIL: 0x%08x\n", snapshot->reg.ring_tail);
> 	drm_printf(p, "\tRING_CTL: 0x%08x\n", snapshot->reg.ring_ctl);
>diff --git a/drivers/gpu/drm/xe/xe_hw_engine_types.h b/drivers/gpu/drm/xe/xe_hw_engine_types.h
>index 5f4b67acba991..b2f64b92a6362 100644
>--- a/drivers/gpu/drm/xe/xe_hw_engine_types.h
>+++ b/drivers/gpu/drm/xe/xe_hw_engine_types.h
>@@ -188,9 +188,7 @@ struct xe_hw_engine_snapshot {
> 		/** @reg.ring_hws_pga: RING_HWS_PGA */
> 		u32 ring_hws_pga;
> 		/** @reg.ring_start: RING_START */
>-		u32 ring_start;
>-		/** @reg.ring_start_udw: RING_START_UDW */
>-		u32 ring_start_udw;
>+		u64 ring_start;
> 		/** @reg.ring_head: RING_HEAD */
> 		u32 ring_head;
> 		/** @reg.ring_tail: RING_TAIL */
>-- 
>2.45.0
>