[PATCH] drm/xe: flush gtt before signalling user fence on media engines

[Matthew Brost]

On Tue, May 21, 2024 at 05:23:46PM +0200, Andrzej Hajda wrote:
> Tests show that user fence signalling requires kind of write barrier,
> otherwise not all writes performed by the workload will be available
> to userspace.
> 
> Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/1488
> Signed-off-by: Andrzej Hajda <andrzej.hajda at intel.com>

Fixes tag?

With a proper fixes tag:
Reviewed-by: Matthew Brost <matthew.brost at intel.com>

> ---
>  drivers/gpu/drm/xe/xe_ring_ops.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c
> index a3ca718456f6..eb36901f96ff 100644
> --- a/drivers/gpu/drm/xe/xe_ring_ops.c
> +++ b/drivers/gpu/drm/xe/xe_ring_ops.c
> @@ -293,13 +293,13 @@ static void __emit_job_gen12_video(struct xe_sched_job *job, struct xe_lrc *lrc,
>  
>  	i = emit_bb_start(batch_addr, ppgtt_flag, dw, i);
>  
> +	i = emit_flush_imm_ggtt(xe_lrc_seqno_ggtt_addr(lrc), seqno, false, dw, i);
> +
>  	if (job->user_fence.used)
>  		i = emit_store_imm_ppgtt_posted(job->user_fence.addr,
>  						job->user_fence.value,
>  						dw, i);
>  
> -	i = emit_flush_imm_ggtt(xe_lrc_seqno_ggtt_addr(lrc), seqno, false, dw, i);
> -
>  	i = emit_user_interrupt(dw, i);
>  
>  	xe_gt_assert(gt, i <= MAX_JOB_SIZE_DW);
> 
> ---
> base-commit: 188ced1e0ff892f0948f20480e2e0122380ae46d
> change-id: 20240521-xu_flush_vcs_before_ufence-a7b45d94cf33
> 
> Best regards,
> -- 
> Andrzej Hajda <andrzej.hajda at intel.com>
>