[PATCH v3 1/1] drm/xe/uapi: Expose the L3 bank mask

[Matt Roper]

On Tue, May 21, 2024 at 08:31:12AM -0700, Souza, Jose wrote:
> On Tue, 2024-04-16 at 14:50 +0000, Francois Dugast wrote:
> > The L3 bank mask is already generated and stored internally with
> > the rest of the GT topology. In user space, the compute runtime
> > now needs this information to be added to the device properties
> > therefore the topology mask query is extended to provide a new
> > mask which represents the L3 banks enabled on the GT.
> > 
> > The changes in the compute runtime are ready and approved, see
> > link below.
> > 
> > v2: Rewrite commit message and add a link to the compute
> >     runtime PR (Francois Dugast)
> > 
> 
> Reviewed-by: José Roberto de Souza <jose.souza at intel.com>

Applied to drm-xe-next.  Thanks for the patch and reviews.


Matt

> 
> > Cc: Matt Roper <matthew.d.roper at intel.com>
> > Cc: Robert Krzemien <robert.krzemien at intel.com>
> > Cc: Mateusz Jablonski <mateusz.jablonski at intel.com>
> > Link: https://github.com/intel/compute-runtime/pull/722
> > Signed-off-by: Francois Dugast <francois.dugast at intel.com>
> > ---
> >  drivers/gpu/drm/xe/xe_query.c | 9 ++++++++-
> >  include/uapi/drm/xe_drm.h     | 2 ++
> >  2 files changed, 10 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/xe/xe_query.c b/drivers/gpu/drm/xe/xe_query.c
> > index df407d73e5f5..6e0170bdae44 100644
> > --- a/drivers/gpu/drm/xe/xe_query.c
> > +++ b/drivers/gpu/drm/xe/xe_query.c
> > @@ -454,9 +454,10 @@ static int query_hwconfig(struct xe_device *xe,
> >  static size_t calc_topo_query_size(struct xe_device *xe)
> >  {
> >  	return xe->info.gt_count *
> > -		(3 * sizeof(struct drm_xe_query_topology_mask) +
> > +		(4 * sizeof(struct drm_xe_query_topology_mask) +
> >  		 sizeof_field(struct xe_gt, fuse_topo.g_dss_mask) +
> >  		 sizeof_field(struct xe_gt, fuse_topo.c_dss_mask) +
> > +		 sizeof_field(struct xe_gt, fuse_topo.l3_bank_mask) +
> >  		 sizeof_field(struct xe_gt, fuse_topo.eu_mask_per_dss));
> >  }
> >  
> > @@ -510,6 +511,12 @@ static int query_gt_topology(struct xe_device *xe,
> >  		if (err)
> >  			return err;
> >  
> > +		topo.type = DRM_XE_TOPO_L3_BANK;
> > +		err = copy_mask(&query_ptr, &topo, gt->fuse_topo.l3_bank_mask,
> > +				sizeof(gt->fuse_topo.l3_bank_mask));
> > +		if (err)
> > +			return err;
> > +
> >  		topo.type = DRM_XE_TOPO_EU_PER_DSS;
> >  		err = copy_mask(&query_ptr, &topo,
> >  				gt->fuse_topo.eu_mask_per_dss,
> > diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
> > index 1446c3bae515..d7b0903c22b2 100644
> > --- a/include/uapi/drm/xe_drm.h
> > +++ b/include/uapi/drm/xe_drm.h
> > @@ -508,6 +508,7 @@ struct drm_xe_query_gt_list {
> >   *    containing the following in mask:
> >   *    ``DSS_COMPUTE    ff ff ff ff 00 00 00 00``
> >   *    means 32 DSS are available for compute.
> > + *  - %DRM_XE_TOPO_L3_BANK - To query the mask of enabled L3 banks
> >   *  - %DRM_XE_TOPO_EU_PER_DSS - To query the mask of Execution Units (EU)
> >   *    available per Dual Sub Slices (DSS). For example a query response
> >   *    containing the following in mask:
> > @@ -520,6 +521,7 @@ struct drm_xe_query_topology_mask {
> >  
> >  #define DRM_XE_TOPO_DSS_GEOMETRY	1
> >  #define DRM_XE_TOPO_DSS_COMPUTE		2
> > +#define DRM_XE_TOPO_L3_BANK		3
> >  #define DRM_XE_TOPO_EU_PER_DSS		4
> >  	/** @type: type of mask */
> >  	__u16 type;
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation