✓ CI.checkpatch: success for Enable Coarse Power Gating (rev2)

[Patchwork]

== Series Details ==

Series: Enable Coarse Power Gating (rev2)
URL   : https://patchwork.freedesktop.org/series/134001/
State : success

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
51ce9f6cd981d42d7467409d7dbc559a450abc1e
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 0d636eb7a8a1f85e165bc5b0b77492771250498b
Author: Riana Tauro <riana.tauro at intel.com>
Date:   Fri May 24 12:39:16 2024 +0530

    drm/xe: Enable Coarse Power Gating
    
    Enable power gating for all units and sub-pipes that
    are disabled by default.
    
    v2: change the init function name
        use symmetric calls for enable/disable pg
        re-pharase commit message (Rodrigo)
        modify the sub-pipe power gating condition
    
    v3: set hysteresis value for render and media
        when GuC PC is disabled
        skip CPG for PVC (Vinay)
    
    v4: rebase
    
    Signed-off-by: Riana Tauro <riana.tauro at intel.com>
    Reviewed-by: Rodrigo Vivi <rodrigo.vivi at intel.com> #v2
+ /mt/dim checkpatch 573842e9ab57ccd8d6bb68ad55ed2e012e3d5d2f drm-intel
6930cace1c15 drm/xe: Standardize power gate registers
0d636eb7a8a1 drm/xe: Enable Coarse Power Gating