[PATCH v2 01/17] drm/i915/dmc_wl: Use i915_mmio_reg_offset() instead of reg.reg

[Jani Nikula]

On Wed, 06 Nov 2024, Gustavo Sousa <gustavo.sousa at intel.com> wrote:
> The macro i915_mmio_reg_offset() is the proper interface to get a
> register's offset. Use that instead of looking directly at reg.reg.
>
> Cc: Jani Nikula <jani.nikula at intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa at intel.com>

Reviewed-by: Jani Nikula <jani.nikula at intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dmc_wl.c | 11 ++++++-----
>  1 file changed, 6 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.c b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
> index 5634ff07269d..05892a237d3a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc_wl.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
> @@ -91,14 +91,15 @@ static void intel_dmc_wl_work(struct work_struct *work)
>  	spin_unlock_irqrestore(&wl->lock, flags);
>  }
>  
> -static bool intel_dmc_wl_check_range(u32 address)
> +static bool intel_dmc_wl_check_range(i915_reg_t reg)
>  {
>  	int i;
>  	bool wl_needed = false;
> +	u32 offset = i915_mmio_reg_offset(reg);
>  
>  	for (i = 0; i < ARRAY_SIZE(lnl_wl_range); i++) {
> -		if (address >= lnl_wl_range[i].start &&
> -		    address <= lnl_wl_range[i].end) {
> +		if (offset >= lnl_wl_range[i].start &&
> +		    offset <= lnl_wl_range[i].end) {
>  			wl_needed = true;
>  			break;
>  		}
> @@ -191,7 +192,7 @@ void intel_dmc_wl_get(struct intel_display *display, i915_reg_t reg)
>  	if (!__intel_dmc_wl_supported(display))
>  		return;
>  
> -	if (!intel_dmc_wl_check_range(reg.reg))
> +	if (!intel_dmc_wl_check_range(reg))
>  		return;
>  
>  	spin_lock_irqsave(&wl->lock, flags);
> @@ -239,7 +240,7 @@ void intel_dmc_wl_put(struct intel_display *display, i915_reg_t reg)
>  	if (!__intel_dmc_wl_supported(display))
>  		return;
>  
> -	if (!intel_dmc_wl_check_range(reg.reg))
> +	if (!intel_dmc_wl_check_range(reg))
>  		return;
>  
>  	spin_lock_irqsave(&wl->lock, flags);

-- 
Jani Nikula, Intel