✓ CI.checkpatch: success for drm/i915/cx0: Set power state to ready only on owned PHY lanes (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915/cx0: Set power state to ready only on owned PHY lanes (rev4)
URL   : https://patchwork.freedesktop.org/series/138990/
State : success

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
30ab6715fc09baee6cc14cb3c89ad8858688d474
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit ad0b3ee5f750f32094da1fd863e923b358d64729
Author: Vamsi Krishna Brahmajosyula <vamsikrishna.brahmajosyula at gmail.com>
Date:   Tue Nov 12 18:18:52 2024 +0530

    drm/i915/cx0: Set power state to ready only on owned PHY lanes
    
    In DP alt mode, when pin assignment is D, only one PHY lane is owned
    by the display. intel_cx0pll_enable currently performs a power state
    ready on both the lanes in all cases.
    
    Address the following todo to perfom power state ready on owned lanes.
        TODO: For DP alt mode use only one lane.
    
    Tested on Meteor Lake-P [Intel Arc Graphics] with DP alt mode.
    
    Signed-off-by: Vamsi Krishna Brahmajosyula <vamsikrishna.brahmajosyula at gmail.com>
+ /mt/dim checkpatch 26f5fe99791def93b32e27e79e71dbd0666c117b drm-intel
ad0b3ee5f750 drm/i915/cx0: Set power state to ready only on owned PHY lanes