[PATCH] drm/xe/vf: Print assumed values of the MOCS entries if VF

[Matt Roper]

On Fri, Nov 15, 2024 at 10:00:25PM +0100, Michal Wajdeczko wrote:
> VF drivers can't access the MOCS registers so their values can't
> be printed as part of the gt0/mocs debugfs attribute, but since
> MOCS settings are part of the Bspec and SLA between PF and VFs,
> we can print assumed MOCS values instead.

Is it actually useful to anyone for us to fake these values?  It feels
like changing the semantics (printing what the values _should_ be
instead of what they necessarily are) could just cause confusion if
someone is trying to debug a real bug.  Would it be better to just print
an "unavailable" message (or just not register the debugfs at all) when
running in a VF?


Matt

> 
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko at intel.com>
> Cc: Matt Roper <matthew.d.roper at intel.com>
> ---
>  drivers/gpu/drm/xe/xe_mocs.c | 42 +++++++++++++++++++++++++++++-------
>  1 file changed, 34 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_mocs.c b/drivers/gpu/drm/xe/xe_mocs.c
> index 54d199b5cfb2..9ad5366f4370 100644
> --- a/drivers/gpu/drm/xe/xe_mocs.c
> +++ b/drivers/gpu/drm/xe/xe_mocs.c
> @@ -257,6 +257,14 @@ static const struct xe_mocs_entry gen12_mocs_desc[] = {
>  		   L3_1_UC)
>  };
>  
> +static u32 get_entry_control(const struct xe_mocs_info *info, unsigned int index);
> +static u32 get_combined_entry_l3cc(const struct xe_mocs_info *info, unsigned int index);
> +
> +static bool regs_are_not_available(struct xe_gt *gt)
> +{
> +	return IS_SRIOV_VF(gt_to_xe(gt));
> +}
> +
>  static bool regs_are_mcr(struct xe_gt *gt)
>  {
>  	struct xe_device *xe = gt_to_xe(gt);
> @@ -275,7 +283,9 @@ static void xelp_lncf_dump(struct xe_mocs_info *info, struct xe_gt *gt, struct d
>  	drm_printf(p, "LNCFCMOCS[idx] = [ESC, SCC, L3CC] (value)\n\n");
>  
>  	for (i = 0, j = 0; i < (info->num_mocs_regs + 1) / 2; i++, j++) {
> -		if (regs_are_mcr(gt))
> +		if (regs_are_not_available(gt))
> +			reg_val = get_combined_entry_l3cc(info, i);
> +		else if (regs_are_mcr(gt))
>  			reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_LNCFCMOCS(i));
>  		else
>  			reg_val = xe_mmio_read32(&gt->mmio, XELP_LNCFCMOCS(i));
> @@ -307,7 +317,9 @@ static void xelp_mocs_dump(struct xe_mocs_info *info, unsigned int flags,
>  		drm_printf(p, "GLOB_MOCS[idx] = [LeCC, TC, LRUM, AOM, RSC, SCC, PFM, SCF, CoS, SSE] (value)\n\n");
>  
>  		for (i = 0; i < info->num_mocs_regs; i++) {
> -			if (regs_are_mcr(gt))
> +			if (regs_are_not_available(gt))
> +				reg_val = get_entry_control(info, i);
> +			else if (regs_are_mcr(gt))
>  				reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_GLOBAL_MOCS(i));
>  			else
>  				reg_val = xe_mmio_read32(&gt->mmio, XELP_GLOBAL_MOCS(i));
> @@ -380,7 +392,9 @@ static void xehp_lncf_dump(struct xe_mocs_info *info, unsigned int flags,
>  	drm_printf(p, "LNCFCMOCS[idx] = [UCL3LOOKUP, GLBGO, L3CC] (value)\n\n");
>  
>  	for (i = 0, j = 0; i < (info->num_mocs_regs + 1) / 2; i++, j++) {
> -		if (regs_are_mcr(gt))
> +		if (regs_are_not_available(gt))
> +			reg_val = get_combined_entry_l3cc(info, i);
> +		else if (regs_are_mcr(gt))
>  			reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_LNCFCMOCS(i));
>  		else
>  			reg_val = xe_mmio_read32(&gt->mmio, XELP_LNCFCMOCS(i));
> @@ -425,7 +439,9 @@ static void pvc_mocs_dump(struct xe_mocs_info *info, unsigned int flags, struct
>  	drm_printf(p, "LNCFCMOCS[idx] = [ L3CC ] (value)\n\n");
>  
>  	for (i = 0, j = 0; i < (info->num_mocs_regs + 1) / 2; i++, j++) {
> -		if (regs_are_mcr(gt))
> +		if (regs_are_not_available(gt))
> +			reg_val = get_combined_entry_l3cc(info, i);
> +		else if (regs_are_mcr(gt))
>  			reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_LNCFCMOCS(i));
>  		else
>  			reg_val = xe_mmio_read32(&gt->mmio, XELP_LNCFCMOCS(i));
> @@ -507,7 +523,9 @@ static void mtl_mocs_dump(struct xe_mocs_info *info, unsigned int flags,
>  	drm_printf(p, "GLOB_MOCS[idx] = [IG_PAT, L4_CACHE_POLICY] (value)\n\n");
>  
>  	for (i = 0; i < info->num_mocs_regs; i++) {
> -		if (regs_are_mcr(gt))
> +		if (regs_are_not_available(gt))
> +			reg_val = get_entry_control(info, i);
> +		else if (regs_are_mcr(gt))
>  			reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_GLOBAL_MOCS(i));
>  		else
>  			reg_val = xe_mmio_read32(&gt->mmio, XELP_GLOBAL_MOCS(i));
> @@ -550,7 +568,9 @@ static void xe2_mocs_dump(struct xe_mocs_info *info, unsigned int flags,
>  	drm_printf(p, "GLOB_MOCS[idx] = [IG_PAT, L3_CLOS, L3_CACHE_POLICY, L4_CACHE_POLICY] (value)\n\n");
>  
>  	for (i = 0; i < info->num_mocs_regs; i++) {
> -		if (regs_are_mcr(gt))
> +		if (regs_are_not_available(gt))
> +			reg_val = get_entry_control(info, i);
> +		else if (regs_are_mcr(gt))
>  			reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_GLOBAL_MOCS(i));
>  		else
>  			reg_val = xe_mmio_read32(&gt->mmio, XELP_GLOBAL_MOCS(i));
> @@ -713,6 +733,13 @@ static u32 l3cc_combine(u16 low, u16 high)
>  	return low | (u32)high << 16;
>  }
>  
> +static u32 get_combined_entry_l3cc(const struct xe_mocs_info *info,
> +				   unsigned int index)
> +{
> +	return l3cc_combine(get_entry_l3cc(info, 2 * index),
> +			    get_entry_l3cc(info, 2 * index + 1));
> +}
> +
>  static void init_l3cc_table(struct xe_gt *gt,
>  			    const struct xe_mocs_info *info)
>  {
> @@ -722,8 +749,7 @@ static void init_l3cc_table(struct xe_gt *gt,
>  	mocs_dbg(gt, "l3cc entries: %d\n", info->num_mocs_regs);
>  
>  	for (i = 0; i < (info->num_mocs_regs + 1) / 2; i++) {
> -		l3cc = l3cc_combine(get_entry_l3cc(info, 2 * i),
> -				    get_entry_l3cc(info, 2 * i + 1));
> +		l3cc = get_combined_entry_l3cc(info, i);
>  
>  		mocs_dbg(gt, "LNCFCMOCS[%d] 0x%x 0x%x\n", i,
>  			 XELP_LNCFCMOCS(i).addr, l3cc);
> -- 
> 2.43.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation