[PATCH] drm/xe: Sort again the info flags

[Matthew Auld]

On 18/11/2024 22:33, Lucas De Marchi wrote:
> Those flags are supposed to be kept sorted alphabetically. Unfortunately
> it's a constant battle as new flags are added to the end or at random
> places. Sort it again.
> 
> v2: Include the other non-has_* 1-bit flags in the sort
> 
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi at intel.com> # v1
> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
> ---
>   drivers/gpu/drm/xe/xe_device_types.h | 32 ++++++++++++++++------------
>   1 file changed, 18 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> index 8592f1b02db11..8b2b12daa49dd 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -294,14 +294,21 @@ struct xe_device {
>   		/** @info.va_bits: Maximum bits of a virtual address */
>   		u8 va_bits;

Should we not document somewhere here that the below should be kept sorted?

>   
> -		/** @info.is_dgfx: is discrete device */
> -		u8 is_dgfx:1;
> -		/** @info.has_asid: Has address space ID */
> -		u8 has_asid:1;
>   		/** @info.force_execlist: Forced execlist submission */
>   		u8 force_execlist:1;
> +
> +		/** @info.has_asid: Has address space ID */
> +		u8 has_asid:1;
> +		/** @info.has_atomic_enable_pte_bit: Device has atomic enable PTE bit */
> +		u8 has_atomic_enable_pte_bit:1;
> +		/** @info.has_device_atomics_on_smem: Supports device atomics on SMEM */
> +		u8 has_device_atomics_on_smem:1;
>   		/** @info.has_flat_ccs: Whether flat CCS metadata is used */
>   		u8 has_flat_ccs:1;
> +		/** @info.has_heci_cscfi: device has heci cscfi */
> +		u8 has_heci_cscfi:1;
> +		/** @info.has_heci_gscfi: device has heci gscfi */
> +		u8 has_heci_gscfi:1;
>   		/** @info.has_llc: Device has a shared CPU+GPU last level cache */
>   		u8 has_llc:1;
>   		/** @info.has_mmio_ext: Device has extra MMIO address range */
> @@ -312,6 +319,10 @@ struct xe_device {
>   		u8 has_sriov:1;
>   		/** @info.has_usm: Device has unified shared memory support */
>   		u8 has_usm:1;
> +
> +		/** @info.is_dgfx: is discrete device */
> +		u8 is_dgfx:1;
> +
>   		/**
>   		 * @info.probe_display: Probe display hardware.  If set to
>   		 * false, the driver will behave as if there is no display
> @@ -321,20 +332,13 @@ struct xe_device {
>   		 * state the firmware or bootloader left it in.
>   		 */
>   		u8 probe_display:1;
> +
> +		/** @info.skip_guc_pc: Skip GuC based PM feature init */
> +		u8 skip_guc_pc:1;
>   		/** @info.skip_mtcfg: skip Multi-Tile configuration from MTCFG register */
>   		u8 skip_mtcfg:1;
>   		/** @info.skip_pcode: skip access to PCODE uC */
>   		u8 skip_pcode:1;
> -		/** @info.has_heci_gscfi: device has heci gscfi */
> -		u8 has_heci_gscfi:1;
> -		/** @info.has_heci_cscfi: device has heci cscfi */
> -		u8 has_heci_cscfi:1;
> -		/** @info.skip_guc_pc: Skip GuC based PM feature init */
> -		u8 skip_guc_pc:1;
> -		/** @info.has_atomic_enable_pte_bit: Device has atomic enable PTE bit */
> -		u8 has_atomic_enable_pte_bit:1;
> -		/** @info.has_device_atomics_on_smem: Supports device atomics on SMEM */
> -		u8 has_device_atomics_on_smem:1;
>   	} info;
>   
>   	/** @irq: device interrupt state */