✓ CI.checkpatch: success for drm/xe/guc: Fix missing init value and add register order check (rev3)

[Patchwork]

== Series Details ==

Series: drm/xe/guc: Fix missing init value and add register order check (rev3)
URL   : https://patchwork.freedesktop.org/series/140889/
State : success

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
30ab6715fc09baee6cc14cb3c89ad8858688d474
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 30cadd51cfeb254efcbe5ada8331e39e82daf079
Author: Zhanjun Dong <zhanjun.dong at intel.com>
Date:   Tue Nov 19 15:13:56 2024 -0800

    drm/xe/guc: Fix missing init value and add register order check
    
    Fix missing initial value for last_value.
    For GuC capture register definition, it is required to define 64bit
    register in a pair of 2 consecutive 32bit register entries, low first,
    then hi. Add code to check this order.
    
    Fixes: ecb633646391 ("drm/xe/guc: Plumb GuC-capture into dev coredump")
    
    Signed-off-by: Zhanjun Dong <zhanjun.dong at intel.com>
    Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>
    
    Changes from prior revs:
     v4:- Fix warn on condition and remove skipping
     v3:- Move break inside brace
     v2:- Correct the fix tag pointed commit
          Add examples in comments for warning
          Add 1 missing hi condition check
+ /mt/dim checkpatch ccf64319402f90f68549e2047a7f985a46436e41 drm-intel
30cadd51cfeb drm/xe/guc: Fix missing init value and add register order check