✗ CI.checkpatch: warning for use hw support for min/interim ddb allocation for async flip (rev2)

[Patchwork]

== Series Details ==

Series: use hw support for min/interim ddb allocation for async flip (rev2)
URL   : https://patchwork.freedesktop.org/series/140927/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
30ab6715fc09baee6cc14cb3c89ad8858688d474
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 70a2e2b080fd50a1c7b9170e8037b2d416c2f6a1
Author: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com>
Date:   Thu Nov 21 13:27:26 2024 +0200

    drm/i915/xe3: Use hw support for min/interim ddb allocations for async flip
    
    Xe3 is capable of switching automatically to min ddb allocation
    (not using any extra blocks) or interim SAGV-adjusted allocation
    in case if async flip is used. Introduce the minimum and interim
    ddb allocation configuration for that purpose. Also i915 is
    replaced with intel_display within the patch's context
    
    v2: update min/interim ddb declarations and handling (Ville)
        update to register definitions styling
        consolidation of minimal wm0 check with min DDB check
    
    Bspec: 69880, 72053
    Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com>
    Signed-off-by: Vinod Govindapillai <vinod.govindapillai at intel.com>
+ /mt/dim checkpatch e46649e7764a9f6868ccbcba7b8b23b413303380 drm-intel
3cff11f4fe3d drm/i915/display: update to plane_wm register access function
c93b20a5beef drm/i915/display: update to relative data rate handling
70a2e2b080fd drm/i915/xe3: Use hw support for min/interim ddb allocations for async flip
-:133: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#133: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:389:
+							_PLANE_MIN_BUF_CFG_1_A, _PLANE_MIN_BUF_CFG_1_B, \

-:134: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#134: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:390:
+							_PLANE_MIN_BUF_CFG_2_A, _PLANE_MIN_BUF_CFG_2_B)

-:139: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#139: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:395:
+#define	  PLANE_INTERIM_DBUF_BLOCKS(val)	REG_FIELD_PREP(PLANE_INTERIM_DBUF_BLOCKS_MASK, (val))

total: 0 errors, 3 warnings, 0 checks, 357 lines checked