✓ CI.Patch_applied: success for Plane Color Pipeline support for Intel platforms

[Patchwork]

== Series Details ==

Series: Plane Color Pipeline support for Intel platforms
URL   : https://patchwork.freedesktop.org/series/141788/
State : success

== Summary ==

=== Applying kernel patches on branch 'drm-tip' with base: ===
Base commit: ef0147fcb01d drm-tip: 2024y-11m-26d-12h-47m-19s UTC integration manifest
=== git am output follows ===
Applying: drm: color pipeline base work
Applying: drm: Add support for 3x3 CTM
Applying: drm: Add Enhanced LUT precision structure
Applying: drm: Add Color lut range attributes
Applying: drm: Add Color ops capability property
Applying: drm: Define helper to create color ops capability property
Applying: drm: Add 1D LUT multi-segmented color op
Applying: drm: Define helper for adding capability property for 1D LUT MULTSEG
Applying: drm: Add helper to initialize segmented 1D LUT
Applying: drm/i915: Add identifiers for intel color blocks
Applying: drm/i915: Add intel_color_op
Applying: drm/i915/color: Add helper to create intel colorop
Applying: drm/i915/color: Create a transfer function color pipeline
Applying: drm/i915/color: Add and attach COLORPIPELINE plane property
Applying: drm/i915/color: Add framework to set colorop
Applying: drm/i915/color: Add callbacks to set plane CTM
Applying: drm/i915/color: Add new color callbacks for Xelpd
Applying: drm/i915/color: Add plane CTM callback for D13 and beyond
Applying: drm/i915: Add register definitions for Plane Degamma
Applying: drm/i915/color: Add framework to program PRE/POST CSC LUT
Applying: drm/i915: Add register definitions for Plane Post CSC
Applying: drm/i915/color: Program Pre-CSC registers
Applying: drm/i915/xelpd: Program Plane Post CSC Registers
Applying: drm/i915/color: Enable Plane Color Pipelines
Applying: drm/doc/rfc: Add documentation for multi-segmented 1D LUT