✗ CI.checkpatch: warning for x86/apic: Stop the TSC Deadline timer during lapic timer shutdown

Patchwork patchwork at emeril.freedesktop.org
Mon Oct 7 18:20:50 UTC 2024


== Series Details ==

Series: x86/apic: Stop the TSC Deadline timer during lapic timer shutdown
URL   : https://patchwork.freedesktop.org/series/139636/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
30ab6715fc09baee6cc14cb3c89ad8858688d474
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit bf51cea6de6dd1820b78d8df05f57b289429d1b9
Author: Zhang Rui <rui.zhang at intel.com>
Date:   Mon Oct 7 19:22:42 2024 +0530

    x86/apic: Stop the TSC Deadline timer during lapic timer shutdown
    
    This is a core-for-CI patch for
    https://lore.kernel.org/all/20240929063521.17284-1-rui.zhang@intel.com/
    
    According to Intel SDM, for the local APIC timer,
    1. "The initial-count register is a read-write register. A write of 0 to
       the initial-count register effectively stops the local APIC timer, in
       both one-shot and periodic mode."
    2. "In TSC deadline mode, writes to the initial-count register are
       ignored; and current-count register always reads 0. Instead, timer
       behavior is controlled using the IA32_TSC_DEADLINE MSR."
       "In TSC-deadline mode, writing 0 to the IA32_TSC_DEADLINE MSR disarms
       the local-APIC timer."
    
    Current code in lapic_timer_shutdown() writes 0 to the initial-count
    register. This stops the local APIC timer for one-shot and periodic mode
    only. In TSC deadline mode, the timer is not properly stopped.
    
    Some CPUs are affected by this and they are woke up by the armed timer
    in s2idle in TSC deadline mode.
    
    Stop the TSC deadline timer in lapic_timer_shutdown() by writing 0 to
    MSR_IA32_TSC_DEADLINE.
    
    Fixes: 279f1461432c ("x86: apic: Use tsc deadline for oneshot when available")
    Link: https://lore.kernel.org/all/20240929063521.17284-1-rui.zhang@intel.com/
    References: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12344
    Signed-off-by: Zhang Rui <rui.zhang at intel.com>
    Signed-off-by: Karthik Poosa <karthik.poosa at intel.com>
+ /mt/dim checkpatch 39a016b276ce8adac629cc6c31892d0b7d2af634 drm-intel
bf51cea6de6d x86/apic: Stop the TSC Deadline timer during lapic timer shutdown
-:32: WARNING:COMMIT_LOG_USE_LINK: Unknown link reference 'References:', use 'Link:' or 'Closes:' instead
#32: 
References: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12344

total: 0 errors, 1 warnings, 0 checks, 10 lines checked




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