✓ CI.checkpatch: success for drm/i915: gen2 stuff

[Patchwork]

== Series Details ==

Series: drm/i915: gen2 stuff
URL   : https://patchwork.freedesktop.org/series/139727/
State : success

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
30ab6715fc09baee6cc14cb3c89ad8858688d474
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit e8c01e07444811f0a91c41b98d8fb88fca88b742
Author: Ville Syrjälä <ville.syrjala at linux.intel.com>
Date:   Wed Oct 9 00:43:49 2024 +0300

    drm/i915/pmu: Add support for gen2
    
    Implement pmu support for gen2 so that one can use intel_gpu_top
    on it once again.
    
    Gen2 lacks MI_MODE/MODE_IDLE so we'll have to do a bit more work
    to determine the state of the engine:
    - to determine if the ring contains unconsumed data we can simply
      compare RING_TAIL vs. RING_HEAD
    - also check RING_HEAD vs. ACTHD to catch cases where the hardware
      is still executing a batch buffer but the ring head has already
      caught up with the tail. Not entirely sure if that's actually
      possible or not, but maybe it can happen if the batch buffer is
      initiated from the very end of the ring? But even if not strictly
      necessary there's no real harm in checking anyway.
    - MI_WAIT_FOR_EVENT can be detected via a dedicated bit in RING_HEAD
    
    Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
+ /mt/dim checkpatch 8752b50cc6ea4e90f3caa68dd1cc169112ac4b34 drm-intel
a87c3a9d3876 drm/i915/gt: Nuke gen2_irq_{enable,disable}()
20883744a025 drm/i915/gt: s/gen3/gen2/
57c6ac2c4983 drm/i915/irq: s/gen3/gen2/
e8c01e074448 drm/i915/pmu: Add support for gen2