✓ CI.checkpatch: success for drm/xe/mmap: Add mmap support for PCI memory barrier

[Patchwork]

== Series Details ==

Series: drm/xe/mmap: Add mmap support for PCI memory barrier
URL   : https://patchwork.freedesktop.org/series/139769/
State : success

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
30ab6715fc09baee6cc14cb3c89ad8858688d474
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit c5a5959aa6dd06cb96af072b18c8b49c2cb1fe4c
Author: Tejas Upadhyay <tejas.upadhyay at intel.com>
Date:   Wed Oct 9 15:40:04 2024 +0530

    drm/xe/mmap: Add mmap support for PCI memory barrier
    
    In order to avoid having userspace to use MI_MEM_FENCE,
    we are adding a mechanism for userspace to generate a
    PCI memory barrier with low overhead (avoiding IOCTL call).
    
    This is implemented by memory-mapping a page as uncached
    that is backed by MMIO on the dGPU and thus allowing userspace
    to do memory write to the page without invoking an IOCTL.
    We are selecting the MMIO so that it is not accessible from
    the PCI bus so that the MMIO writes themselves are ignored,
    but the PCI memory barrier will still take action as the MMIO
    filtering will happen after the memory barrier effect.
    
    When we detect special defined offset in mmap(), We are mapping
    4K page which contains the last of page of doorbell MMIO range
    to userspace for same purpose.
    
    Note: Test coverage for this is added by IGT
          https://patchwork.freedesktop.org/patch/618931/  here.
    
    Signed-off-by: Tejas Upadhyay <tejas.upadhyay at intel.com>
+ /mt/dim checkpatch f1561e6c62b5b5c3fe0276f2fbe7325e0d7c262d drm-intel
c5a5959aa6dd drm/xe/mmap: Add mmap support for PCI memory barrier